-- Copyright (C) 2018  Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Intel Program License 
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors.  Please
-- refer to the applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition"

-- DATE "03/08/2021 09:19:51"

-- 
-- Device: Altera EP4CE115F29C7 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	hard_block IS
    PORT (
	devoe : IN std_logic;
	devclrn : IN std_logic;
	devpor : IN std_logic
	);
END hard_block;

-- Design Ports Information
-- ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF hard_block IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;

BEGIN

ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
END structure;


LIBRARY ALTERA;
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	dbg_port_top IS
    PORT (
	clk : IN std_logic;
	res_n : IN std_logic;
	rx : IN std_logic;
	tx : OUT std_logic;
	switches : OUT std_logic_vector(17 DOWNTO 0);
	keys : OUT std_logic_vector(3 DOWNTO 0);
	ledr : IN std_logic_vector(17 DOWNTO 0);
	ledg : IN std_logic_vector(8 DOWNTO 0);
	dsc : OUT std_logic;
	gfx_instr : OUT std_logic_vector(7 DOWNTO 0);
	gfx_instr_wr : OUT std_logic;
	gfx_instr_full : IN std_logic;
	gfx_data : OUT std_logic_vector(15 DOWNTO 0);
	gfx_data_wr : OUT std_logic;
	gfx_data_full : IN std_logic;
	nes_buttons_btn_up : OUT std_logic;
	nes_buttons_btn_down : OUT std_logic;
	nes_buttons_btn_left : OUT std_logic;
	nes_buttons_btn_right : OUT std_logic;
	nes_buttons_btn_start : OUT std_logic;
	nes_buttons_btn_select : OUT std_logic;
	nes_buttons_btn_a : OUT std_logic;
	nes_buttons_btn_b : OUT std_logic;
	nes_clk : IN std_logic;
	nes_data : OUT std_logic;
	nes_latch : IN std_logic;
	hex0 : IN std_logic_vector(6 DOWNTO 0);
	hex1 : IN std_logic_vector(6 DOWNTO 0);
	hex2 : IN std_logic_vector(6 DOWNTO 0);
	hex3 : IN std_logic_vector(6 DOWNTO 0);
	hex4 : IN std_logic_vector(6 DOWNTO 0);
	hex5 : IN std_logic_vector(6 DOWNTO 0);
	hex6 : IN std_logic_vector(6 DOWNTO 0);
	hex7 : IN std_logic_vector(6 DOWNTO 0)
	);
END dbg_port_top;

-- Design Ports Information
-- tx	=>  Location: PIN_AB10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[0]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[1]	=>  Location: PIN_G17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[2]	=>  Location: PIN_C7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[3]	=>  Location: PIN_G19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[4]	=>  Location: PIN_M28,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[5]	=>  Location: PIN_F8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[6]	=>  Location: PIN_AC10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[7]	=>  Location: PIN_B11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[8]	=>  Location: PIN_J14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[9]	=>  Location: PIN_E17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[10]	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[11]	=>  Location: PIN_A11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[12]	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[13]	=>  Location: PIN_M8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[14]	=>  Location: PIN_J12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[15]	=>  Location: PIN_J5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[16]	=>  Location: PIN_AF13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- switches[17]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- keys[0]	=>  Location: PIN_G2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- keys[1]	=>  Location: PIN_M2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- keys[2]	=>  Location: PIN_J17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- keys[3]	=>  Location: PIN_A10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- dsc	=>  Location: PIN_L6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[0]	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[1]	=>  Location: PIN_B18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[2]	=>  Location: PIN_C15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[3]	=>  Location: PIN_D17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[4]	=>  Location: PIN_AH12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[5]	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[6]	=>  Location: PIN_D16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr[7]	=>  Location: PIN_F15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr_wr	=>  Location: PIN_A18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[0]	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[1]	=>  Location: PIN_D12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[2]	=>  Location: PIN_C12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[3]	=>  Location: PIN_J15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[4]	=>  Location: PIN_G20,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[5]	=>  Location: PIN_G16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[6]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[7]	=>  Location: PIN_A12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[8]	=>  Location: PIN_AD11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[9]	=>  Location: PIN_AE14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[10]	=>  Location: PIN_AC11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[11]	=>  Location: PIN_AB13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[12]	=>  Location: PIN_N21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[13]	=>  Location: PIN_Y13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[14]	=>  Location: PIN_AF14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data[15]	=>  Location: PIN_AD12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data_wr	=>  Location: PIN_G22,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_up	=>  Location: PIN_R2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_down	=>  Location: PIN_D7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_left	=>  Location: PIN_P1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_right	=>  Location: PIN_L1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_start	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_select	=>  Location: PIN_M5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_a	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_buttons_btn_b	=>  Location: PIN_L2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_data	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_instr_full	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- gfx_data_full	=>  Location: PIN_M27,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- res_n	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_latch	=>  Location: PIN_R1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- nes_clk	=>  Location: PIN_R7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex7[4]	=>  Location: PIN_A7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex7[5]	=>  Location: PIN_A8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex7[6]	=>  Location: PIN_D9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex7[0]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex7[3]	=>  Location: PIN_J4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex7[1]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex7[2]	=>  Location: PIN_J10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex6[4]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex6[5]	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex6[6]	=>  Location: PIN_C11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- rx	=>  Location: PIN_P2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex6[0]	=>  Location: PIN_B10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex6[3]	=>  Location: PIN_K3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex6[1]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex6[2]	=>  Location: PIN_D11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex5[4]	=>  Location: PIN_E12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex5[5]	=>  Location: PIN_G9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex5[6]	=>  Location: PIN_G8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex5[0]	=>  Location: PIN_B7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex5[3]	=>  Location: PIN_H8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex5[1]	=>  Location: PIN_G11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex5[2]	=>  Location: PIN_H10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex4[4]	=>  Location: PIN_C10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex4[5]	=>  Location: PIN_C8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex4[6]	=>  Location: PIN_C9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex4[0]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex4[3]	=>  Location: PIN_K4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex4[1]	=>  Location: PIN_E7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex4[2]	=>  Location: PIN_G10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex3[4]	=>  Location: PIN_K1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex3[5]	=>  Location: PIN_D6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex3[6]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex3[0]	=>  Location: PIN_E8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex3[3]	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex3[1]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex3[2]	=>  Location: PIN_B6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex2[4]	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex2[5]	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex2[6]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex2[0]	=>  Location: PIN_F17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[16]	=>  Location: PIN_J16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex2[3]	=>  Location: PIN_A4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex2[1]	=>  Location: PIN_G14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[17]	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex2[2]	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex1[4]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[12]	=>  Location: PIN_F14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[15]	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex1[5]	=>  Location: PIN_AB12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[13]	=>  Location: PIN_H16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex1[6]	=>  Location: PIN_H13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[14]	=>  Location: PIN_R4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex1[0]	=>  Location: PIN_H17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[8]	=>  Location: PIN_H21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[8]	=>  Location: PIN_L3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex1[3]	=>  Location: PIN_D13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[11]	=>  Location: PIN_H14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex1[1]	=>  Location: PIN_C14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[9]	=>  Location: PIN_D14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex1[2]	=>  Location: PIN_C16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[10]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex0[4]	=>  Location: PIN_AC12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[4]	=>  Location: PIN_H19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[4]	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[7]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[7]	=>  Location: PIN_AH11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex0[5]	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[5]	=>  Location: PIN_N3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[5]	=>  Location: PIN_K7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex0[6]	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[6]	=>  Location: PIN_AE13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[6]	=>  Location: PIN_B8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex0[0]	=>  Location: PIN_D8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[0]	=>  Location: PIN_AG11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[0]	=>  Location: PIN_U3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex0[3]	=>  Location: PIN_L8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[3]	=>  Location: PIN_G7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[3]	=>  Location: PIN_J19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex0[1]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[1]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[1]	=>  Location: PIN_H15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- hex0[2]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledr[2]	=>  Location: PIN_G18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledg[2]	=>  Location: PIN_G13,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF dbg_port_top IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_res_n : std_logic;
SIGNAL ww_rx : std_logic;
SIGNAL ww_tx : std_logic;
SIGNAL ww_switches : std_logic_vector(17 DOWNTO 0);
SIGNAL ww_keys : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_ledr : std_logic_vector(17 DOWNTO 0);
SIGNAL ww_ledg : std_logic_vector(8 DOWNTO 0);
SIGNAL ww_dsc : std_logic;
SIGNAL ww_gfx_instr : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_gfx_instr_wr : std_logic;
SIGNAL ww_gfx_instr_full : std_logic;
SIGNAL ww_gfx_data : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_gfx_data_wr : std_logic;
SIGNAL ww_gfx_data_full : std_logic;
SIGNAL ww_nes_buttons_btn_up : std_logic;
SIGNAL ww_nes_buttons_btn_down : std_logic;
SIGNAL ww_nes_buttons_btn_left : std_logic;
SIGNAL ww_nes_buttons_btn_right : std_logic;
SIGNAL ww_nes_buttons_btn_start : std_logic;
SIGNAL ww_nes_buttons_btn_select : std_logic;
SIGNAL ww_nes_buttons_btn_a : std_logic;
SIGNAL ww_nes_buttons_btn_b : std_logic;
SIGNAL ww_nes_clk : std_logic;
SIGNAL ww_nes_data : std_logic;
SIGNAL ww_nes_latch : std_logic;
SIGNAL ww_hex0 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex1 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex2 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex3 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex4 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex5 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex6 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex7 : std_logic_vector(6 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \res_n~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \tx~output_o\ : std_logic;
SIGNAL \switches[0]~output_o\ : std_logic;
SIGNAL \switches[1]~output_o\ : std_logic;
SIGNAL \switches[2]~output_o\ : std_logic;
SIGNAL \switches[3]~output_o\ : std_logic;
SIGNAL \switches[4]~output_o\ : std_logic;
SIGNAL \switches[5]~output_o\ : std_logic;
SIGNAL \switches[6]~output_o\ : std_logic;
SIGNAL \switches[7]~output_o\ : std_logic;
SIGNAL \switches[8]~output_o\ : std_logic;
SIGNAL \switches[9]~output_o\ : std_logic;
SIGNAL \switches[10]~output_o\ : std_logic;
SIGNAL \switches[11]~output_o\ : std_logic;
SIGNAL \switches[12]~output_o\ : std_logic;
SIGNAL \switches[13]~output_o\ : std_logic;
SIGNAL \switches[14]~output_o\ : std_logic;
SIGNAL \switches[15]~output_o\ : std_logic;
SIGNAL \switches[16]~output_o\ : std_logic;
SIGNAL \switches[17]~output_o\ : std_logic;
SIGNAL \keys[0]~output_o\ : std_logic;
SIGNAL \keys[1]~output_o\ : std_logic;
SIGNAL \keys[2]~output_o\ : std_logic;
SIGNAL \keys[3]~output_o\ : std_logic;
SIGNAL \dsc~output_o\ : std_logic;
SIGNAL \gfx_instr[0]~output_o\ : std_logic;
SIGNAL \gfx_instr[1]~output_o\ : std_logic;
SIGNAL \gfx_instr[2]~output_o\ : std_logic;
SIGNAL \gfx_instr[3]~output_o\ : std_logic;
SIGNAL \gfx_instr[4]~output_o\ : std_logic;
SIGNAL \gfx_instr[5]~output_o\ : std_logic;
SIGNAL \gfx_instr[6]~output_o\ : std_logic;
SIGNAL \gfx_instr[7]~output_o\ : std_logic;
SIGNAL \gfx_instr_wr~output_o\ : std_logic;
SIGNAL \gfx_data[0]~output_o\ : std_logic;
SIGNAL \gfx_data[1]~output_o\ : std_logic;
SIGNAL \gfx_data[2]~output_o\ : std_logic;
SIGNAL \gfx_data[3]~output_o\ : std_logic;
SIGNAL \gfx_data[4]~output_o\ : std_logic;
SIGNAL \gfx_data[5]~output_o\ : std_logic;
SIGNAL \gfx_data[6]~output_o\ : std_logic;
SIGNAL \gfx_data[7]~output_o\ : std_logic;
SIGNAL \gfx_data[8]~output_o\ : std_logic;
SIGNAL \gfx_data[9]~output_o\ : std_logic;
SIGNAL \gfx_data[10]~output_o\ : std_logic;
SIGNAL \gfx_data[11]~output_o\ : std_logic;
SIGNAL \gfx_data[12]~output_o\ : std_logic;
SIGNAL \gfx_data[13]~output_o\ : std_logic;
SIGNAL \gfx_data[14]~output_o\ : std_logic;
SIGNAL \gfx_data[15]~output_o\ : std_logic;
SIGNAL \gfx_data_wr~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_up~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_down~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_left~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_right~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_start~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_select~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_a~output_o\ : std_logic;
SIGNAL \nes_buttons_btn_b~output_o\ : std_logic;
SIGNAL \nes_data~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~9_combout\ : std_logic;
SIGNAL \res_n~input_o\ : std_logic;
SIGNAL \res_n~inputclkctrl_outclk\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector27~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector26~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector25~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector6~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector7~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|Equal1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|write_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~9_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector8~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\ : std_logic;
SIGNAL \rx~input_o\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|rx_sync_vector[1]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|rx_sync_vector[2]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.GOTO_MIDDLE_OF_START_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~10\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~11_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~12\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~13_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~14\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~15_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~16\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~17_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~18\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~20_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~21\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~22_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~23\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~24_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~25\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~26_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|Equal0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_rx_rd~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[7]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[6]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out[6]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~41_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~20_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[5]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[4]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[3]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[1]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~_wirecell_combout\ : std_logic;
SIGNAL \~GND~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out[1]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out[2]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out[4]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out[5]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out[7]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~27_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~28_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~21_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~29_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~30_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~19_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~22_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~26_combout\ : std_logic;
SIGNAL \dbg_port_inst|Mux0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~14_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~39_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~40_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~15_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~33_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[11]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~34_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~17_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~31_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~32_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~16_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~35_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~36_combout\ : std_logic;
SIGNAL \dbg_port_inst|Mux0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Mux0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector7~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~9_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector7~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.WAIT_READ~q\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.READ_COMMAND~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector12~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector3~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector7~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector3~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.READ_OPERATION~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~17_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector31~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~10_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|LessThan4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~16_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|value[1]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|value[1]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|value[1]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector32~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector33~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector34~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~75_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector6~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.IDLE~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|value[2]~_wirecell_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width[5]~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width[5]~9_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~15_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector71~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_start~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~9_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~10_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~11_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Add3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[0]~12_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|shift_amount[0]~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Add1~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Add1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|shift_amount[2]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Add1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|shift_amount[3]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.IDLE~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.IDLE~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.IDLE~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.IDLE~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|done~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector6~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector5~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state.COMPLETE_ABORT~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|abort~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|write_address[3]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state~32_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|Equal0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector8~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|Mux4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector9~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.PRINT_ERROR~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state~30_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector8~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector12~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_start~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state.IDLE~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|first_char~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|expect_leading_space~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|first_char~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|first_char~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|first_char~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[5]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~11_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[0]~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[0]~10_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~15_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[1]~12_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[0]~17_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[0]~15_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[0]~16_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[0]~18_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~1\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~1\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[1]~13_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[1]~14_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~3\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~1\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector14~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~3\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector14~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add4~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~3\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~5\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~5\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector13~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector13~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~5\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~7\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~7\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~9\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~10_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~7\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~9\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~10_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector11~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector11~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[2]~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[2]~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[2]~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|current_length[2]~9_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector12~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add1~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector12~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add2~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Add0~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector12~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~12_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_max_length[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_max_length[0]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_max_length[0]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_max_length[0]~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|LessThan11~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector15~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|LessThan11~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_width[0]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|LessThan11~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector13~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_max_length[4]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|LessThan11~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~13_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~14_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector7~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector7~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state.COMPLETE_ERROR~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|parse_error~q\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state~31_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector21~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_str[1][4]~q\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Selector5~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Selector0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|state.IDLE~q\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|idx[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Selector4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Selector3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|state~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Selector2~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|state.COMPLETE~q\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|done~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector10~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.WAIT_PRINT_STR~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~9_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.IDLE~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_rx_rd~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~23_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~24_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~18_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~37_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~38_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|process_0~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state~20_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state~21_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state~22_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|expect_leading_space~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|expect_leading_space~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state.READ_CHAR~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|rx_rd~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|rx_rd~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector6~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|state.COMPLETE_DONE~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|done~q\ : std_logic;
SIGNAL \dbg_port_inst|Selector11~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state.PRINT_OK~q\ : std_logic;
SIGNAL \dbg_port_inst|fsm_state~33_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_start~q\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Selector1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Selector1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|tx_wr~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|tx_wr~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|tx_wr~q\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_wr~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~10\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~11_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~12\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~13_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~14\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~15_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~16\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~17_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~18\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~19_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~20\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~21_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~22\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~23_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~24\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[8]~25_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector2~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.SEND_START_BIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector20~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_str[0][1]~q\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux6~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux6~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector66~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector65~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|first_digit_mask~0_combout\ : std_logic;
SIGNAL \hex2[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|Equal0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~27_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[22]~17_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[28]~90_combout\ : std_logic;
SIGNAL \hex2[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~33_combout\ : std_logic;
SIGNAL \hex0[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector28~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Equal13~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Selector11~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|switches[0]~0_combout\ : std_logic;
SIGNAL \ledr[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[6]~54_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[6]~53_combout\ : std_logic;
SIGNAL \dbg_port_inst|Equal18~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[4]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~66_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~67_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[6]~feeder_combout\ : std_logic;
SIGNAL \ledg[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[4]~57_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[60]~14_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[4]~58_combout\ : std_logic;
SIGNAL \dbg_port_inst|keys[2]~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|keys[0]~0_combout\ : std_logic;
SIGNAL \ledr[2]~input_o\ : std_logic;
SIGNAL \ledg[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[2]~77_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[2]~78_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~86_combout\ : std_logic;
SIGNAL \hex0[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~87_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~88_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[2]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[2]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[3]~82_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[3]~94_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector61~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector57~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector24~0_combout\ : std_logic;
SIGNAL \hex1[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~51_combout\ : std_logic;
SIGNAL \ledr[10]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~52_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[16]~30_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[16]~91_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector53~0_combout\ : std_logic;
SIGNAL \ledr[14]~input_o\ : std_logic;
SIGNAL \hex1[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~40_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector20~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|switches[14]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~93_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector49~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector45~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector41~0_combout\ : std_logic;
SIGNAL \hex3[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~24_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector37~0_combout\ : std_logic;
SIGNAL \hex3[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~20_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector33~0_combout\ : std_logic;
SIGNAL \hex4[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|Equal0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[60]~89_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector29~0_combout\ : std_logic;
SIGNAL \hex4[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector25~0_combout\ : std_logic;
SIGNAL \hex5[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[42]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector21~0_combout\ : std_logic;
SIGNAL \hex5[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[46]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector17~0_combout\ : std_logic;
SIGNAL \hex6[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector13~0_combout\ : std_logic;
SIGNAL \hex6[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector9~0_combout\ : std_logic;
SIGNAL \hex7[2]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[58]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector5~0_combout\ : std_logic;
SIGNAL \hex7[6]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[62]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\ : std_logic;
SIGNAL \hex7[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[57]~feeder_combout\ : std_logic;
SIGNAL \hex6[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[49]~feeder_combout\ : std_logic;
SIGNAL \hex5[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[45]~feeder_combout\ : std_logic;
SIGNAL \hex5[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[41]~feeder_combout\ : std_logic;
SIGNAL \hex4[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[37]~feeder_combout\ : std_logic;
SIGNAL \hex4[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[33]~feeder_combout\ : std_logic;
SIGNAL \ledr[1]~input_o\ : std_logic;
SIGNAL \ledg[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~83_combout\ : std_logic;
SIGNAL \hex0[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~84_combout\ : std_logic;
SIGNAL \dbg_port_inst|keys[1]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~85_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[1]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[1]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector62~0_combout\ : std_logic;
SIGNAL \hex0[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector29~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[5]~feeder_combout\ : std_logic;
SIGNAL \ledr[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~64_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~65_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[5]~feeder_combout\ : std_logic;
SIGNAL \ledg[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector58~0_combout\ : std_logic;
SIGNAL \ledr[9]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector25~0_combout\ : std_logic;
SIGNAL \hex1[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~49_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~50_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector54~0_combout\ : std_logic;
SIGNAL \ledr[13]~input_o\ : std_logic;
SIGNAL \hex1[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector21~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~38_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~39_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector50~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector17~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|switches[17]~feeder_combout\ : std_logic;
SIGNAL \hex2[1]~input_o\ : std_logic;
SIGNAL \ledr[17]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~32_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~92_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector46~0_combout\ : std_logic;
SIGNAL \hex2[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~26_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector42~0_combout\ : std_logic;
SIGNAL \hex3[1]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~23_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector38~0_combout\ : std_logic;
SIGNAL \hex3[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~19_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector34~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector30~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector26~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector22~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector18~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector14~0_combout\ : std_logic;
SIGNAL \hex6[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector10~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector6~0_combout\ : std_logic;
SIGNAL \hex7[5]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector2~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\ : std_logic;
SIGNAL \hex6[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[51]~feeder_combout\ : std_logic;
SIGNAL \hex5[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[43]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[23]~18_combout\ : std_logic;
SIGNAL \hex3[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~22_combout\ : std_logic;
SIGNAL \hex2[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~31_combout\ : std_logic;
SIGNAL \ledr[3]~input_o\ : std_logic;
SIGNAL \ledg[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~79_combout\ : std_logic;
SIGNAL \hex0[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~80_combout\ : std_logic;
SIGNAL \dbg_port_inst|keys[3]~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~81_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[3]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[3]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector60~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~62_combout\ : std_logic;
SIGNAL \ledg[7]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector27~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[7]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[7]~59_combout\ : std_logic;
SIGNAL \ledr[7]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[7]~60_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[7]~61_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[7]~63_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector56~0_combout\ : std_logic;
SIGNAL \ledr[11]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector23~0_combout\ : std_logic;
SIGNAL \hex1[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~47_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~48_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector52~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector19~0_combout\ : std_logic;
SIGNAL \ledr[15]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[15]~36_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[15]~37_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector48~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector44~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector40~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector36~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector32~0_combout\ : std_logic;
SIGNAL \hex4[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector28~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector24~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector20~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector16~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector12~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector8~0_combout\ : std_logic;
SIGNAL \hex7[3]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[59]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector64~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\ : std_logic;
SIGNAL \hex7[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[60]~feeder_combout\ : std_logic;
SIGNAL \hex6[4]~input_o\ : std_logic;
SIGNAL \hex6[0]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[48]~feeder_combout\ : std_logic;
SIGNAL \hex5[0]~input_o\ : std_logic;
SIGNAL \hex4[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[36]~feeder_combout\ : std_logic;
SIGNAL \hex4[0]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[32]~feeder_combout\ : std_logic;
SIGNAL \hex3[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~16_combout\ : std_logic;
SIGNAL \hex3[0]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~21_combout\ : std_logic;
SIGNAL \hex0[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector30~0_combout\ : std_logic;
SIGNAL \ledr[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[4]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~55_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~56_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[4]~feeder_combout\ : std_logic;
SIGNAL \ledg[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|Equal15~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|dsc_intern[0]~0_combout\ : std_logic;
SIGNAL \ledr[0]~input_o\ : std_logic;
SIGNAL \ledg[0]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~69_combout\ : std_logic;
SIGNAL \hex0[0]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~70_combout\ : std_logic;
SIGNAL \dbg_port_inst|keys[0]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~71_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~72_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|Equal17~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_input_wr~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_input_wr~q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~1_combout\ : std_logic;
SIGNAL \gfx_data_full~input_o\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|rd_valid~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Equal1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\ : std_logic;
SIGNAL \gfx_instr_full~input_o\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_input_wr~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_input_wr~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_input_wr~q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|rd~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~68_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes_buttons_intern[0]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~73_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~74_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[0]~76_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector63~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector59~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector26~0_combout\ : std_logic;
SIGNAL \ledg[8]~input_o\ : std_logic;
SIGNAL \hex1[0]~input_o\ : std_logic;
SIGNAL \ledr[8]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[8]~41_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[8]~42_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[8]~43_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~44_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[8]~45_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value[8]~46_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector55~0_combout\ : std_logic;
SIGNAL \ledr[12]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector22~0_combout\ : std_logic;
SIGNAL \hex1[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~34_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~35_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector51~0_combout\ : std_logic;
SIGNAL \ledr[16]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|Selector18~0_combout\ : std_logic;
SIGNAL \hex2[0]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~28_combout\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~29_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector47~0_combout\ : std_logic;
SIGNAL \hex2[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|hex_writer_value~25_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector43~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector39~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector35~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector31~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector27~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector23~0_combout\ : std_logic;
SIGNAL \hex5[4]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector19~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector15~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector11~0_combout\ : std_logic;
SIGNAL \hex7[0]~input_o\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector7~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|first_digit_mask[0]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector88~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|tx_data[1]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_data[1]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[1]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[3]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~23_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~24_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[0]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector89~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux7~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux7~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_data[0]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~_wirecell_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux5~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector87~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_data[2]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector86~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|tx_data[3]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux4~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_data[3]~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector85~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_data[4]~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|tx_data[5]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|str_writer_inst|Mux1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_data[5]~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|ci_hex_writer_inst|Selector83~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|uart_tx_data[6]~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~29_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~27_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~28_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~41_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[7]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~20_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~39_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~40_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector18~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~37_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~38_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector19~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~35_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~36_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector20~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~33_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~34_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector21~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~31_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~32_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector22~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector23~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14_q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~22_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~26_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector24~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~44_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~52_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~68_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~60_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~12_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~20_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~79_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~80_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~45_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~69_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~61_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~82_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~21_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~13_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~84_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~85_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~46_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~70_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~62_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~87_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~22_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~14_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~89_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~90_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~55_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~47_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~71_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~63_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~92_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~15_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~93_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~94_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~95_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~40_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~16_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~98_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~99_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~64_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~72_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~48_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~56_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~97_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~100_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~49_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~57_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~73_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~102_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~17_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~103_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~104_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~105_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~50_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~58_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~74_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~66_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~107_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~18_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~109_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~110_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~51_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~59_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~75_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~67_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~112_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~19_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~113_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~114_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~115_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_instr_rd_ack~combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~42_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~43_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[2]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~41_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~_wirecell_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~_wirecell_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~40_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~45_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[15]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~46_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~47_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~48_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~49_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~50_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~51_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~52_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~53_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[23]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~54_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~55_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[26]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~56_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~57_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[28]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~58_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[27]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~59_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[30]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a8\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~60_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[29]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~61_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[32]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a9\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~62_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[31]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~63_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[34]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[33]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a10\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~64_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~65_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[36]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[35]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a11\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~66_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~67_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[38]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a12\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~68_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~69_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[39]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[40]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a13\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~70_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~71_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[42]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a14\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~72_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~73_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a15\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~74_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[44]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[43]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~75_combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_rd_ack~combout\ : std_logic;
SIGNAL \nes_latch~input_o\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\ : std_logic;
SIGNAL \nes_clk~input_o\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~7_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~5_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~1\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~9\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~10_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~11\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~12_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~3\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~5\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~6_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~7\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~8_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_right~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_b~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_up~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_select~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[0]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[1]~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector10~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[7]~3_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector11~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector12~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector13~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector14~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector15~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector16~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|Selector17~0_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[0]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[1]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[2]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[3]~feeder_combout\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|str_writer_inst|idx\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\ : std_logic_vector(0 TO 24);
SIGNAL \dbg_port_inst|str_writer_inst|tx_data\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|rx_sync_vector\ : std_logic_vector(1 TO 2);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\ : std_logic_vector(0 TO 24);
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|hex_writer_value\ : std_logic_vector(63 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\ : std_logic_vector(8 DOWNTO 0);
SIGNAL \dbg_port_inst|hex_reader_inst|current_length\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \dbg_port_inst|hex_reader_max_length\ : std_logic_vector(4 DOWNTO 0);
SIGNAL \dbg_port_inst|ci_hex_writer_inst|tx_data\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|hex_reader_inst|value\ : std_logic_vector(17 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_int\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|hex_writer_width\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \dbg_port_inst|ci_hex_writer_inst|value_buffer\ : std_logic_vector(63 DOWNTO 0);
SIGNAL \dbg_port_inst|switches\ : std_logic_vector(17 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|receiver_inst|data_out\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|keys\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|dsc_intern\ : std_logic_vector(0 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|ci_hex_writer_inst|shift_amount\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|nes_buttons_intern\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\ : std_logic_vector(8 DOWNTO 0);
SIGNAL \dbg_port_inst|write_address\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\ : std_logic_vector(0 TO 44);
SIGNAL \dbg_port_inst|hex_reader_inst|ALT_INV_value\ : std_logic_vector(0 DOWNTO 0);
SIGNAL \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_DATA~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|ALT_INV_done~q\ : std_logic;
SIGNAL \dbg_port_inst|nes:nes_controller_emulator_inst|ALT_INV_output_delay\ : std_logic_vector(3 DOWNTO 3);
SIGNAL \dbg_port_inst|ALT_INV_dsc_intern\ : std_logic_vector(0 DOWNTO 0);
SIGNAL \dbg_port_inst|ALT_INV_keys\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_ADDRESS~q\ : std_logic;
SIGNAL \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|transmitter_fifo|ALT_INV_rd_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|serial_port_inst|receiver_fifo|ALT_INV_rd_int~combout\ : std_logic;
SIGNAL \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~_wirecell_combout\ : std_logic;

COMPONENT hard_block
    PORT (
	devoe : IN std_logic;
	devclrn : IN std_logic;
	devpor : IN std_logic);
END COMPONENT;

BEGIN

ww_clk <= clk;
ww_res_n <= res_n;
ww_rx <= rx;
tx <= ww_tx;
switches <= ww_switches;
keys <= ww_keys;
ww_ledr <= ledr;
ww_ledg <= ledg;
dsc <= ww_dsc;
gfx_instr <= ww_gfx_instr;
gfx_instr_wr <= ww_gfx_instr_wr;
ww_gfx_instr_full <= gfx_instr_full;
gfx_data <= ww_gfx_data;
gfx_data_wr <= ww_gfx_data_wr;
ww_gfx_data_full <= gfx_data_full;
nes_buttons_btn_up <= ww_nes_buttons_btn_up;
nes_buttons_btn_down <= ww_nes_buttons_btn_down;
nes_buttons_btn_left <= ww_nes_buttons_btn_left;
nes_buttons_btn_right <= ww_nes_buttons_btn_right;
nes_buttons_btn_start <= ww_nes_buttons_btn_start;
nes_buttons_btn_select <= ww_nes_buttons_btn_select;
nes_buttons_btn_a <= ww_nes_buttons_btn_a;
nes_buttons_btn_b <= ww_nes_buttons_btn_b;
ww_nes_clk <= nes_clk;
nes_data <= ww_nes_data;
ww_nes_latch <= nes_latch;
ww_hex0 <= hex0;
ww_hex1 <= hex1;
ww_hex2 <= hex2;
ww_hex3 <= hex3;
ww_hex4 <= hex4;
ww_hex5 <= hex5;
ww_hex6 <= hex6;
ww_hex7 <= hex7;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & 
\dbg_port_inst|hex_reader_inst|value\(15) & \dbg_port_inst|hex_reader_inst|value\(14) & \dbg_port_inst|hex_reader_inst|value\(13) & \dbg_port_inst|hex_reader_inst|value\(12) & \dbg_port_inst|hex_reader_inst|value\(11) & 
\dbg_port_inst|hex_reader_inst|value\(10) & \dbg_port_inst|hex_reader_inst|value\(9) & \dbg_port_inst|hex_reader_inst|value\(8) & \dbg_port_inst|hex_reader_inst|value\(7) & \dbg_port_inst|hex_reader_inst|value\(6) & 
\dbg_port_inst|hex_reader_inst|value\(5) & \dbg_port_inst|hex_reader_inst|value\(4) & \dbg_port_inst|hex_reader_inst|value\(3) & \dbg_port_inst|hex_reader_inst|value\(2) & \dbg_port_inst|hex_reader_inst|value\(1) & 
\dbg_port_inst|hex_reader_inst|value\(0));

\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4) & 
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) & 
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0));

\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\ & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\ & 
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\ & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\ & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~0_combout\ & 
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~_wirecell_combout\);

\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a8\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(8);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a9\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(9);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a10\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(10);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a11\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(11);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a12\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(12);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a13\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(13);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a14\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(14);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a15\ <= \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(15);

\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & \~GND~combout\ & \dbg_port_inst|uart_tx_data[6]~6_combout\ & \dbg_port_inst|uart_tx_data[5]~5_combout\ & \dbg_port_inst|uart_tx_data[4]~4_combout\ & \dbg_port_inst|uart_tx_data[3]~3_combout\ & 
\dbg_port_inst|uart_tx_data[2]~2_combout\ & \dbg_port_inst|uart_tx_data[1]~1_combout\ & \dbg_port_inst|uart_tx_data[0]~0_combout\);

\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3) & 
\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2) & \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1) & \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0));

\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\ & \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\ & 
\dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~2_combout\ & \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~_wirecell_combout\);

\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\ <= \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);

\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & 
gnd & gnd & gnd & gnd & gnd & \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(7) & \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(6) & \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(5) & 
\dbg_port_inst|serial_port_inst|receiver_inst|data_out\(4) & \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(3) & \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(2) & \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(1) & 
\dbg_port_inst|serial_port_inst|receiver_inst|data_out\(0));

\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3) & \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2) & 
\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1) & \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0));

\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\ & \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\ & 
\dbg_port_inst|serial_port_inst|receiver_fifo|Add0~0_combout\ & \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~_wirecell_combout\);

\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\ <= \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);

\res_n~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \res_n~input_o\);
\dbg_port_inst|hex_reader_inst|ALT_INV_value\(0) <= NOT \dbg_port_inst|hex_reader_inst|value\(0);
\dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_DATA~q\ <= NOT \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\;
\dbg_port_inst|hex_reader_inst|ALT_INV_done~q\ <= NOT \dbg_port_inst|hex_reader_inst|done~q\;
\dbg_port_inst|nes:nes_controller_emulator_inst|ALT_INV_output_delay\(3) <= NOT \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(3);
\dbg_port_inst|ALT_INV_dsc_intern\(0) <= NOT \dbg_port_inst|dsc_intern\(0);
\dbg_port_inst|ALT_INV_keys\(3) <= NOT \dbg_port_inst|keys\(3);
\dbg_port_inst|ALT_INV_keys\(2) <= NOT \dbg_port_inst|keys\(2);
\dbg_port_inst|ALT_INV_keys\(1) <= NOT \dbg_port_inst|keys\(1);
\dbg_port_inst|ALT_INV_keys\(0) <= NOT \dbg_port_inst|keys\(0);
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\ <= NOT \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~combout\;
\dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_ADDRESS~q\ <= NOT \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\;
\dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\ <= NOT \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\;
\dbg_port_inst|serial_port_inst|transmitter_fifo|ALT_INV_rd_int~combout\ <= NOT \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\;
\dbg_port_inst|serial_port_inst|receiver_fifo|ALT_INV_rd_int~combout\ <= NOT \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\;
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~_wirecell_combout\ <= NOT \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~_wirecell_combout\;
auto_generated_inst : hard_block
PORT MAP (
	devoe => ww_devoe,
	devclrn => ww_devclrn,
	devpor => ww_devpor);

-- Location: IOOBUF_X38_Y0_N9
\tx~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~1_combout\,
	devoe => ww_devoe,
	o => \tx~output_o\);

-- Location: IOOBUF_X0_Y59_N23
\switches[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(0),
	devoe => ww_devoe,
	o => \switches[0]~output_o\);

-- Location: IOOBUF_X83_Y73_N23
\switches[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(1),
	devoe => ww_devoe,
	o => \switches[1]~output_o\);

-- Location: IOOBUF_X16_Y73_N23
\switches[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(2),
	devoe => ww_devoe,
	o => \switches[2]~output_o\);

-- Location: IOOBUF_X69_Y73_N16
\switches[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(3),
	devoe => ww_devoe,
	o => \switches[3]~output_o\);

-- Location: IOOBUF_X115_Y45_N16
\switches[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(4),
	devoe => ww_devoe,
	o => \switches[4]~output_o\);

-- Location: IOOBUF_X11_Y73_N9
\switches[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(5),
	devoe => ww_devoe,
	o => \switches[5]~output_o\);

-- Location: IOOBUF_X38_Y0_N2
\switches[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(6),
	devoe => ww_devoe,
	o => \switches[6]~output_o\);

-- Location: IOOBUF_X42_Y73_N9
\switches[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(7),
	devoe => ww_devoe,
	o => \switches[7]~output_o\);

-- Location: IOOBUF_X49_Y73_N23
\switches[8]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(8),
	devoe => ww_devoe,
	o => \switches[8]~output_o\);

-- Location: IOOBUF_X67_Y73_N23
\switches[9]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(9),
	devoe => ww_devoe,
	o => \switches[9]~output_o\);

-- Location: IOOBUF_X0_Y48_N2
\switches[10]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(10),
	devoe => ww_devoe,
	o => \switches[10]~output_o\);

-- Location: IOOBUF_X42_Y73_N2
\switches[11]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(11),
	devoe => ww_devoe,
	o => \switches[11]~output_o\);

-- Location: IOOBUF_X45_Y73_N9
\switches[12]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(12),
	devoe => ww_devoe,
	o => \switches[12]~output_o\);

-- Location: IOOBUF_X0_Y45_N16
\switches[13]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(13),
	devoe => ww_devoe,
	o => \switches[13]~output_o\);

-- Location: IOOBUF_X40_Y73_N9
\switches[14]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(14),
	devoe => ww_devoe,
	o => \switches[14]~output_o\);

-- Location: IOOBUF_X0_Y50_N23
\switches[15]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(15),
	devoe => ww_devoe,
	o => \switches[15]~output_o\);

-- Location: IOOBUF_X42_Y0_N16
\switches[16]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(16),
	devoe => ww_devoe,
	o => \switches[16]~output_o\);

-- Location: IOOBUF_X0_Y47_N16
\switches[17]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|switches\(17),
	devoe => ww_devoe,
	o => \switches[17]~output_o\);

-- Location: IOOBUF_X0_Y55_N9
\keys[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|ALT_INV_keys\(0),
	devoe => ww_devoe,
	o => \keys[0]~output_o\);

-- Location: IOOBUF_X0_Y44_N16
\keys[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|ALT_INV_keys\(1),
	devoe => ww_devoe,
	o => \keys[1]~output_o\);

-- Location: IOOBUF_X69_Y73_N2
\keys[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|ALT_INV_keys\(2),
	devoe => ww_devoe,
	o => \keys[2]~output_o\);

-- Location: IOOBUF_X38_Y73_N2
\keys[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|ALT_INV_keys\(3),
	devoe => ww_devoe,
	o => \keys[3]~output_o\);

-- Location: IOOBUF_X0_Y47_N23
\dsc~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|ALT_INV_dsc_intern\(0),
	devoe => ww_devoe,
	o => \dsc~output_o\);

-- Location: IOOBUF_X83_Y73_N9
\gfx_instr[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(0),
	devoe => ww_devoe,
	o => \gfx_instr[0]~output_o\);

-- Location: IOOBUF_X79_Y73_N9
\gfx_instr[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(1),
	devoe => ww_devoe,
	o => \gfx_instr[1]~output_o\);

-- Location: IOOBUF_X58_Y73_N16
\gfx_instr[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(2),
	devoe => ww_devoe,
	o => \gfx_instr[2]~output_o\);

-- Location: IOOBUF_X81_Y73_N9
\gfx_instr[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(3),
	devoe => ww_devoe,
	o => \gfx_instr[3]~output_o\);

-- Location: IOOBUF_X54_Y0_N2
\gfx_instr[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(4),
	devoe => ww_devoe,
	o => \gfx_instr[4]~output_o\);

-- Location: IOOBUF_X60_Y73_N9
\gfx_instr[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(5),
	devoe => ww_devoe,
	o => \gfx_instr[5]~output_o\);

-- Location: IOOBUF_X62_Y73_N23
\gfx_instr[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(6),
	devoe => ww_devoe,
	o => \gfx_instr[6]~output_o\);

-- Location: IOOBUF_X58_Y73_N2
\gfx_instr[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(7),
	devoe => ww_devoe,
	o => \gfx_instr[7]~output_o\);

-- Location: IOOBUF_X79_Y73_N2
\gfx_instr_wr~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_instr_rd_ack~combout\,
	devoe => ww_devoe,
	o => \gfx_instr_wr~output_o\);

-- Location: IOOBUF_X74_Y73_N23
\gfx_data[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(0),
	devoe => ww_devoe,
	o => \gfx_data[0]~output_o\);

-- Location: IOOBUF_X52_Y73_N23
\gfx_data[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(1),
	devoe => ww_devoe,
	o => \gfx_data[1]~output_o\);

-- Location: IOOBUF_X52_Y73_N16
\gfx_data[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(2),
	devoe => ww_devoe,
	o => \gfx_data[2]~output_o\);

-- Location: IOOBUF_X60_Y73_N23
\gfx_data[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(3),
	devoe => ww_devoe,
	o => \gfx_data[3]~output_o\);

-- Location: IOOBUF_X74_Y73_N16
\gfx_data[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(4),
	devoe => ww_devoe,
	o => \gfx_data[4]~output_o\);

-- Location: IOOBUF_X67_Y73_N2
\gfx_data[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(5),
	devoe => ww_devoe,
	o => \gfx_data[5]~output_o\);

-- Location: IOOBUF_X54_Y73_N2
\gfx_data[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(6),
	devoe => ww_devoe,
	o => \gfx_data[6]~output_o\);

-- Location: IOOBUF_X47_Y73_N2
\gfx_data[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(7),
	devoe => ww_devoe,
	o => \gfx_data[7]~output_o\);

-- Location: IOOBUF_X49_Y0_N2
\gfx_data[8]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(8),
	devoe => ww_devoe,
	o => \gfx_data[8]~output_o\);

-- Location: IOOBUF_X49_Y0_N23
\gfx_data[9]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(9),
	devoe => ww_devoe,
	o => \gfx_data[9]~output_o\);

-- Location: IOOBUF_X49_Y0_N9
\gfx_data[10]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(10),
	devoe => ww_devoe,
	o => \gfx_data[10]~output_o\);

-- Location: IOOBUF_X47_Y0_N9
\gfx_data[11]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(11),
	devoe => ww_devoe,
	o => \gfx_data[11]~output_o\);

-- Location: IOOBUF_X115_Y42_N16
\gfx_data[12]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(12),
	devoe => ww_devoe,
	o => \gfx_data[12]~output_o\);

-- Location: IOOBUF_X52_Y0_N9
\gfx_data[13]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(13),
	devoe => ww_devoe,
	o => \gfx_data[13]~output_o\);

-- Location: IOOBUF_X49_Y0_N16
\gfx_data[14]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(14),
	devoe => ww_devoe,
	o => \gfx_data[14]~output_o\);

-- Location: IOOBUF_X47_Y0_N2
\gfx_data[15]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(15),
	devoe => ww_devoe,
	o => \gfx_data[15]~output_o\);

-- Location: IOOBUF_X72_Y73_N23
\gfx_data_wr~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|gfx_data_rd_ack~combout\,
	devoe => ww_devoe,
	o => \gfx_data_wr~output_o\);

-- Location: IOOBUF_X0_Y35_N2
\nes_buttons_btn_up~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(4),
	devoe => ww_devoe,
	o => \nes_buttons_btn_up~output_o\);

-- Location: IOOBUF_X13_Y73_N2
\nes_buttons_btn_down~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(5),
	devoe => ww_devoe,
	o => \nes_buttons_btn_down~output_o\);

-- Location: IOOBUF_X0_Y42_N2
\nes_buttons_btn_left~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(6),
	devoe => ww_devoe,
	o => \nes_buttons_btn_left~output_o\);

-- Location: IOOBUF_X0_Y44_N9
\nes_buttons_btn_right~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(7),
	devoe => ww_devoe,
	o => \nes_buttons_btn_right~output_o\);

-- Location: IOOBUF_X0_Y45_N23
\nes_buttons_btn_start~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(3),
	devoe => ww_devoe,
	o => \nes_buttons_btn_start~output_o\);

-- Location: IOOBUF_X0_Y47_N2
\nes_buttons_btn_select~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(2),
	devoe => ww_devoe,
	o => \nes_buttons_btn_select~output_o\);

-- Location: IOOBUF_X0_Y51_N16
\nes_buttons_btn_a~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(0),
	devoe => ww_devoe,
	o => \nes_buttons_btn_a~output_o\);

-- Location: IOOBUF_X0_Y44_N2
\nes_buttons_btn_b~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes_buttons_intern\(1),
	devoe => ww_devoe,
	o => \nes_buttons_btn_b~output_o\);

-- Location: IOOBUF_X0_Y44_N23
\nes_data~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dbg_port_inst|nes:nes_controller_emulator_inst|ALT_INV_output_delay\(3),
	devoe => ww_devoe,
	o => \nes_data~output_o\);

-- Location: IOIBUF_X0_Y36_N15
\clk~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G4
\clk~inputclkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: LCCOMB_X39_Y45_N10
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~9_combout\ = \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(0) $ (VCC)
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~10\ = CARRY(\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010110101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(0),
	datad => VCC,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~9_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~10\);

-- Location: IOIBUF_X0_Y36_N22
\res_n~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_res_n,
	o => \res_n~input_o\);

-- Location: CLKCTRL_G3
\res_n~inputclkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \res_n~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \res_n~inputclkctrl_outclk\);

-- Location: LCCOMB_X38_Y45_N2
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector27~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector27~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (!\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0) & !\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101001011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector27~0_combout\);

-- Location: FF_X38_Y45_N3
\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector27~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0));

-- Location: LCCOMB_X38_Y45_N16
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector26~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector26~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0) $ 
-- ((\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(1))))) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (((\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(1) & 
-- !\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010100001111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0),
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(1),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector26~0_combout\);

-- Location: FF_X38_Y45_N17
\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector26~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(1));

-- Location: LCCOMB_X38_Y45_N4
\dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0) & \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(0),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(1),
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\);

-- Location: LCCOMB_X38_Y45_N30
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector25~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector25~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\ $ 
-- ((\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2))))) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (((\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2) & 
-- !\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010100001111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector25~0_combout\);

-- Location: FF_X38_Y45_N31
\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector25~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2));

-- Location: LCCOMB_X38_Y45_N20
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector6~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2) & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\ & \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2),
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector6~0_combout\);

-- Location: FF_X38_Y45_N21
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector6~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\);

-- Location: LCCOMB_X38_Y45_N8
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector7~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\) # ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\ & 
-- !\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector7~0_combout\);

-- Location: FF_X38_Y45_N9
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector7~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\);

-- Location: LCCOMB_X38_Y46_N4
\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[0]~0_combout\ = !\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[0]~0_combout\);

-- Location: FF_X38_Y46_N19
\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2));

-- Location: LCCOMB_X38_Y46_N18
\dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~1_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2) $ (((\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) & 
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~1_combout\);

-- Location: FF_X38_Y46_N1
\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3));

-- Location: LCCOMB_X38_Y46_N0
\dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~2_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3) $ (((\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) & \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~2_combout\);

-- Location: LCCOMB_X38_Y46_N6
\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~0_combout\ = !\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~0_combout\);

-- Location: LCCOMB_X35_Y46_N2
\dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\ & \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\);

-- Location: FF_X38_Y46_N7
\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0));

-- Location: LCCOMB_X38_Y46_N16
\dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~2_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1) $ (\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~2_combout\);

-- Location: FF_X38_Y46_N17
\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1));

-- Location: LCCOMB_X38_Y46_N20
\dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(2) $ (((\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1) & 
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(2),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\);

-- Location: FF_X38_Y46_N21
\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(2));

-- Location: LCCOMB_X38_Y46_N26
\dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(3) $ (((\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(2) & \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(2),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(3),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\);

-- Location: FF_X38_Y46_N27
\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(3));

-- Location: LCCOMB_X38_Y46_N2
\dbg_port_inst|serial_port_inst|transmitter_fifo|Equal1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|Equal1~0_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~2_combout\ $ (\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(3))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~2_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(3),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|Equal1~0_combout\);

-- Location: LCCOMB_X38_Y46_N8
\dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1) $ (\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1))))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1) $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100101100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~0_combout\);

-- Location: LCCOMB_X38_Y46_N28
\dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~1_combout\ = (!\dbg_port_inst|serial_port_inst|transmitter_fifo|Equal1~0_combout\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~0_combout\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~1_combout\ $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~1_combout\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|Equal1~0_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(2),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~1_combout\);

-- Location: LCCOMB_X48_Y48_N0
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\);

-- Location: FF_X48_Y48_N1
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(18));

-- Location: LCCOMB_X46_Y47_N28
\dbg_port_inst|serial_port_inst|receiver_fifo|write_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|write_address[0]~0_combout\ = !\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address[0]~0_combout\);

-- Location: LCCOMB_X46_Y44_N6
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~9_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0) $ (VCC)
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~10\ = CARRY(\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010110101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0),
	datad => VCC,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~9_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~10\);

-- Location: LCCOMB_X45_Y43_N24
\dbg_port_inst|serial_port_inst|receiver_inst|Selector8~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector8~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\) # ((\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2) & 
-- ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\) # (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector8~0_combout\);

-- Location: FF_X45_Y43_N25
\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector8~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2));

-- Location: LCCOMB_X45_Y43_N26
\dbg_port_inst|serial_port_inst|receiver_inst|Selector4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ & (((!\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2))) # (!\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~0_combout\);

-- Location: LCCOMB_X46_Y44_N4
\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1) & 
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1_combout\);

-- Location: LCCOMB_X46_Y44_N2
\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3) & (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7) & (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4) & 
-- !\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0_combout\);

-- Location: LCCOMB_X46_Y44_N24
\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1_combout\ & (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8) & 
-- \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\);

-- Location: LCCOMB_X45_Y43_N30
\dbg_port_inst|serial_port_inst|receiver_inst|Selector4~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~1_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector4~0_combout\) # ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\) # 
-- ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\ & !\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111011111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~0_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~1_combout\);

-- Location: FF_X45_Y43_N31
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector4~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\);

-- Location: LCCOMB_X45_Y43_N0
\dbg_port_inst|serial_port_inst|receiver_inst|Selector5~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~1_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\ & (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\ & 
-- \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~1_combout\);

-- Location: FF_X45_Y43_N1
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\);

-- Location: LCCOMB_X46_Y43_N6
\dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\ & !\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010100000101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\);

-- Location: IOIBUF_X0_Y43_N15
\rx~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_rx,
	o => \rx~input_o\);

-- Location: LCCOMB_X45_Y43_N8
\dbg_port_inst|serial_port_inst|rx_sync_vector[1]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|rx_sync_vector[1]~0_combout\ = !\rx~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \rx~input_o\,
	combout => \dbg_port_inst|serial_port_inst|rx_sync_vector[1]~0_combout\);

-- Location: FF_X45_Y43_N9
\dbg_port_inst|serial_port_inst|rx_sync_vector[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|rx_sync_vector[1]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|rx_sync_vector\(1));

-- Location: LCCOMB_X46_Y43_N26
\dbg_port_inst|serial_port_inst|rx_sync_vector[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|rx_sync_vector[2]~feeder_combout\ = \dbg_port_inst|serial_port_inst|rx_sync_vector\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|rx_sync_vector\(1),
	combout => \dbg_port_inst|serial_port_inst|rx_sync_vector[2]~feeder_combout\);

-- Location: FF_X46_Y43_N27
\dbg_port_inst|serial_port_inst|rx_sync_vector[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|rx_sync_vector[2]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|rx_sync_vector\(2));

-- Location: LCCOMB_X46_Y43_N18
\dbg_port_inst|serial_port_inst|receiver_inst|Selector0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector0~0_combout\ = ((!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\ & ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\)))) # (!\dbg_port_inst|serial_port_inst|rx_sync_vector\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111010101110111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|rx_sync_vector\(2),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector0~0_combout\);

-- Location: FF_X46_Y43_N19
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\);

-- Location: LCCOMB_X46_Y43_N16
\dbg_port_inst|serial_port_inst|receiver_inst|Selector1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\ & (((!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\ & 
-- !\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\)) # (!\dbg_port_inst|serial_port_inst|rx_sync_vector\(2)))) # (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\ & 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\ & (!\dbg_port_inst|serial_port_inst|rx_sync_vector\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101100101011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\,
	datac => \dbg_port_inst|serial_port_inst|rx_sync_vector\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~0_combout\);

-- Location: LCCOMB_X46_Y43_N20
\dbg_port_inst|serial_port_inst|receiver_inst|Selector1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~1_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_inst|Selector1~0_combout\) # 
-- ((!\dbg_port_inst|serial_port_inst|rx_sync_vector\(2) & \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\)))) # (!\dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\ & 
-- (((!\dbg_port_inst|serial_port_inst|rx_sync_vector\(2) & \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000111110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~2_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~0_combout\,
	datac => \dbg_port_inst|serial_port_inst|rx_sync_vector\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~1_combout\);

-- Location: FF_X46_Y43_N21
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector1~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\);

-- Location: LCCOMB_X45_Y43_N22
\dbg_port_inst|serial_port_inst|receiver_inst|Selector10~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ & (((\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1) & 
-- \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2))) # (!\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~0_combout\);

-- Location: LCCOMB_X45_Y43_N28
\dbg_port_inst|serial_port_inst|receiver_inst|Selector10~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~1_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector10~0_combout\) # ((!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\ & 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ & \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~1_combout\);

-- Location: FF_X45_Y43_N29
\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector10~1_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0));

-- Location: LCCOMB_X45_Y43_N12
\dbg_port_inst|serial_port_inst|receiver_inst|Selector9~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ & (((\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0)))) # (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ & (((!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~0_combout\);

-- Location: LCCOMB_X45_Y43_N10
\dbg_port_inst|serial_port_inst|receiver_inst|Selector9~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~1_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1) & (\dbg_port_inst|serial_port_inst|receiver_inst|Selector9~0_combout\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1) & (((\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0) & \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010110010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~0_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~1_combout\);

-- Location: FF_X45_Y43_N11
\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector9~1_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1));

-- Location: LCCOMB_X45_Y43_N6
\dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1) & (\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0) & 
-- \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(1),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(0),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\);

-- Location: LCCOMB_X45_Y43_N4
\dbg_port_inst|serial_port_inst|receiver_inst|Selector6~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~1_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2)) # 
-- ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\ & !\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\)))) # (!\dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\ & 
-- (((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\ & !\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100011111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~0_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|bit_cnt\(2),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~1_combout\);

-- Location: FF_X45_Y43_N5
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector6~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\);

-- Location: LCCOMB_X45_Y43_N16
\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~5_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\) # 
-- (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_DATA_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~5_combout\);

-- Location: LCCOMB_X46_Y43_N12
\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~6_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4_combout\ & (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.GOTO_MIDDLE_OF_START_BIT~q\ & 
-- ((!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\) # (!\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000011100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~5_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.GOTO_MIDDLE_OF_START_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~6_combout\);

-- Location: LCCOMB_X46_Y43_N14
\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~7_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~6_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\) # 
-- ((\dbg_port_inst|serial_port_inst|rx_sync_vector\(2))))) # (!\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~6_combout\ & (((\dbg_port_inst|serial_port_inst|rx_sync_vector\(2) & 
-- \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010101000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~6_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\,
	datac => \dbg_port_inst|serial_port_inst|rx_sync_vector\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~7_combout\);

-- Location: LCCOMB_X46_Y43_N10
\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~8_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\ & (\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~7_combout\ & 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ & !\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~7_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~8_combout\);

-- Location: FF_X46_Y43_N11
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.GOTO_MIDDLE_OF_START_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~8_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.GOTO_MIDDLE_OF_START_BIT~q\);

-- Location: LCCOMB_X46_Y44_N26
\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~2_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3) & (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.GOTO_MIDDLE_OF_START_BIT~q\ & 
-- (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4) & \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.GOTO_MIDDLE_OF_START_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~2_combout\);

-- Location: LCCOMB_X46_Y44_N28
\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~3_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5) & (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1) & 
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~3_combout\);

-- Location: LCCOMB_X46_Y44_N30
\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~2_combout\ & (\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~3_combout\ & 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8) & \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~2_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~3_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8),
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4_combout\);

-- Location: LCCOMB_X46_Y43_N22
\dbg_port_inst|serial_port_inst|receiver_inst|Selector3~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~3_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4_combout\ & (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\ & 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\ & !\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|Selector2~4_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~3_combout\);

-- Location: FF_X46_Y43_N23
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector3~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\);

-- Location: LCCOMB_X46_Y43_N0
\dbg_port_inst|serial_port_inst|receiver_inst|WideOr2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\) # ((\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\) # 
-- (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_START_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_START_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\);

-- Location: LCCOMB_X46_Y43_N4
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\ & (\res_n~input_o\ & !\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.IDLE~q\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\);

-- Location: FF_X46_Y44_N7
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~9_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(0));

-- Location: LCCOMB_X46_Y44_N8
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~11_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~10\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1) & ((\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~10\) # (GND)))
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~12\ = CARRY((!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~10\) # (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[0]~10\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~11_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~12\);

-- Location: FF_X46_Y44_N9
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~11_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(1));

-- Location: LCCOMB_X46_Y44_N10
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~13_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2) & (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~12\ $ (GND))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~12\ & VCC))
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~14\ = CARRY((\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2) & !\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~12\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[1]~12\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~13_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~14\);

-- Location: FF_X46_Y44_N11
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~13_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(2));

-- Location: LCCOMB_X46_Y44_N12
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~15_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~14\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3) & ((\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~14\) # (GND)))
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~16\ = CARRY((!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~14\) # (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[2]~14\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~15_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~16\);

-- Location: FF_X46_Y44_N13
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~15_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(3));

-- Location: LCCOMB_X46_Y44_N14
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~17_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4) & (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~16\ $ (GND))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~16\ & VCC))
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~18\ = CARRY((\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4) & !\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~16\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[3]~16\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~17_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~18\);

-- Location: FF_X46_Y44_N15
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~17_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(4));

-- Location: LCCOMB_X46_Y44_N16
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~20\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~20_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~18\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5) & ((\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~18\) # (GND)))
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~21\ = CARRY((!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~18\) # (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[4]~18\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~20_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~21\);

-- Location: FF_X46_Y44_N17
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~20_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(5));

-- Location: LCCOMB_X46_Y44_N18
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~22\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~22_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6) & (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~21\ $ (GND))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~21\ & VCC))
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~23\ = CARRY((\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6) & !\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~21\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[5]~21\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~22_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~23\);

-- Location: FF_X46_Y44_N19
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~22_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(6));

-- Location: LCCOMB_X46_Y44_N20
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~24_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7) & (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~23\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7) & ((\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~23\) # (GND)))
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~25\ = CARRY((!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~23\) # (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[6]~23\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~24_combout\,
	cout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~25\);

-- Location: FF_X46_Y44_N21
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~24_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(7));

-- Location: LCCOMB_X46_Y44_N22
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~26\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~26_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8) $ (!\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~25\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010110100101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8),
	cin => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[7]~25\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~26_combout\);

-- Location: FF_X46_Y44_N23
\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~26_combout\,
	sclr => \dbg_port_inst|serial_port_inst|receiver_inst|WideOr2~combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt[8]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8));

-- Location: LCCOMB_X46_Y44_N0
\dbg_port_inst|serial_port_inst|receiver_inst|Selector5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8) & (\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\ & 
-- (\dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1_combout\ & \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|clk_cnt\(8),
	datab => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.WAIT_STOP_BIT~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~1_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|Equal1~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~0_combout\);

-- Location: FF_X46_Y44_N1
\dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|Selector5~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\);

-- Location: FF_X47_Y43_N27
\dbg_port_inst|serial_port_inst|receiver_inst|data_new\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	sload => VCC,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\);

-- Location: LCCOMB_X47_Y47_N24
\dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~0_combout\ = !\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~0_combout\);

-- Location: LCCOMB_X47_Y43_N8
\dbg_port_inst|serial_port_inst|receiver_fifo|rd_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\ & ((\dbg_port_inst|hex_reader_inst|rx_rd~q\) # (\dbg_port_inst|fsm_rx_rd~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|rx_rd~q\,
	datac => \dbg_port_inst|fsm_rx_rd~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\);

-- Location: FF_X47_Y47_N25
\dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0));

-- Location: LCCOMB_X47_Y47_N26
\dbg_port_inst|serial_port_inst|receiver_fifo|Add0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~0_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1) $ (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~0_combout\);

-- Location: FF_X47_Y47_N27
\dbg_port_inst|serial_port_inst|receiver_fifo|read_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1));

-- Location: FF_X47_Y47_N5
\dbg_port_inst|serial_port_inst|receiver_fifo|read_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(2));

-- Location: LCCOMB_X47_Y47_N4
\dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(2) $ (((\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1) & 
-- \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\);

-- Location: LCCOMB_X46_Y47_N24
\dbg_port_inst|serial_port_inst|receiver_fifo|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~0_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2) $ (((\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1) & 
-- \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~0_combout\);

-- Location: FF_X46_Y47_N25
\dbg_port_inst|serial_port_inst|receiver_fifo|write_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2));

-- Location: LCCOMB_X46_Y47_N18
\dbg_port_inst|serial_port_inst|receiver_fifo|Add1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~1_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3) $ (((\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0) & \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~1_combout\);

-- Location: FF_X46_Y47_N19
\dbg_port_inst|serial_port_inst|receiver_fifo|write_address[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3));

-- Location: FF_X47_Y47_N7
\dbg_port_inst|serial_port_inst|receiver_fifo|read_address[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(3));

-- Location: LCCOMB_X47_Y47_N6
\dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(3) $ (((\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0) & \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(2),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\);

-- Location: LCCOMB_X47_Y43_N28
\dbg_port_inst|serial_port_inst|receiver_fifo|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|Equal0~0_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3) $ (\dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|Equal0~0_combout\);

-- Location: LCCOMB_X47_Y47_N16
\dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1) $ (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1))))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0) & (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000101001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~0_combout\);

-- Location: LCCOMB_X47_Y43_N22
\dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~1_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|Equal0~0_combout\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~0_combout\ & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\ $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|Equal0~0_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~1_combout\);

-- Location: LCCOMB_X47_Y43_N10
\dbg_port_inst|uart_rx_rd\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_rx_rd~combout\ = (\dbg_port_inst|hex_reader_inst|rx_rd~q\) # (\dbg_port_inst|fsm_rx_rd~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|rx_rd~q\,
	datac => \dbg_port_inst|fsm_rx_rd~q\,
	combout => \dbg_port_inst|uart_rx_rd~combout\);

-- Location: LCCOMB_X47_Y43_N12
\dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~2_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\) # ((\dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\ & ((!\dbg_port_inst|uart_rx_rd~combout\) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~1_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\,
	datad => \dbg_port_inst|uart_rx_rd~combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~2_combout\);

-- Location: FF_X47_Y43_N13
\dbg_port_inst|serial_port_inst|receiver_fifo|empty_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_next~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\);

-- Location: LCCOMB_X48_Y47_N28
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[7]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[7]~1_combout\ = !\dbg_port_inst|serial_port_inst|rx_sync_vector\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|rx_sync_vector\(2),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[7]~1_combout\);

-- Location: LCCOMB_X45_Y43_N18
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\ = (\res_n~input_o\ & \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_DATA_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\);

-- Location: FF_X48_Y47_N29
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[7]~1_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(7));

-- Location: LCCOMB_X48_Y47_N2
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[6]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[6]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(7),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[6]~feeder_combout\);

-- Location: FF_X48_Y47_N3
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[6]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(6));

-- Location: LCCOMB_X48_Y47_N26
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[6]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_out[6]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(6),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[6]~feeder_combout\);

-- Location: LCCOMB_X46_Y43_N24
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\ = (\res_n~input_o\ & \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|receiver_state.MIDDLE_OF_STOP_BIT~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\);

-- Location: FF_X48_Y47_N27
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[6]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(6));

-- Location: FF_X49_Y47_N3
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(6),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(21));

-- Location: LCCOMB_X50_Y47_N0
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13feeder_combout\);

-- Location: FF_X50_Y47_N1
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\);

-- Location: LCCOMB_X47_Y43_N16
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~41\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~41_combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\ & (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2) & !\dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~41_combout\);

-- Location: LCCOMB_X47_Y47_N12
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1) & 
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~41_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~41_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\);

-- Location: FF_X50_Y47_N19
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~20\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(6),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~20_q\);

-- Location: LCCOMB_X48_Y47_N0
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[5]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(6),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[5]~feeder_combout\);

-- Location: FF_X48_Y47_N1
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[5]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(5));

-- Location: LCCOMB_X48_Y47_N12
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[4]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(5),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[4]~feeder_combout\);

-- Location: FF_X48_Y47_N13
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[4]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(4));

-- Location: LCCOMB_X48_Y47_N22
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[3]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(4),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[3]~feeder_combout\);

-- Location: FF_X48_Y47_N23
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[3]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(3));

-- Location: FF_X48_Y47_N19
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(3),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(2));

-- Location: LCCOMB_X48_Y47_N16
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[1]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(2),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[1]~feeder_combout\);

-- Location: FF_X48_Y47_N17
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[1]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(1));

-- Location: LCCOMB_X48_Y47_N14
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(1),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~feeder_combout\);

-- Location: FF_X48_Y47_N15
\dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_int[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(0));

-- Location: FF_X48_Y47_N31
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(0),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(0));

-- Location: LCCOMB_X47_Y47_N22
\dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~_wirecell\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~_wirecell_combout\ = !\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address[0]~_wirecell_combout\);

-- Location: LCCOMB_X42_Y47_N20
\~GND\ : cycloneive_lcell_comb
-- Equation(s):
-- \~GND~combout\ = GND

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \~GND~combout\);

-- Location: LCCOMB_X48_Y47_N8
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_out[1]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(1),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[1]~feeder_combout\);

-- Location: FF_X48_Y47_N9
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[1]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(1));

-- Location: LCCOMB_X48_Y47_N10
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_out[2]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(2),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[2]~feeder_combout\);

-- Location: FF_X48_Y47_N11
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[2]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(2));

-- Location: FF_X48_Y47_N7
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(3),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(3));

-- Location: LCCOMB_X48_Y47_N20
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_out[4]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(4),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[4]~feeder_combout\);

-- Location: FF_X48_Y47_N21
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[4]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(4));

-- Location: LCCOMB_X48_Y47_N24
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_out[5]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(5),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[5]~feeder_combout\);

-- Location: FF_X48_Y47_N25
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[5]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(5));

-- Location: LCCOMB_X48_Y47_N4
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_inst|data_out[7]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_int\(7),
	combout => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[7]~feeder_combout\);

-- Location: FF_X48_Y47_N5
\dbg_port_inst|serial_port_inst|receiver_inst|data_out[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[7]~feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_inst|data_out[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(7));

-- Location: M9K_X51_Y47_N0
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0\ : cycloneive_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init0 => X"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	init_file => "db/dbg_port_top.ram0_ci_dp_ram_1c1r1w_12035353.hdl.mif",
	init_file_layout => "port_a",
	logical_ram_name => "dbg_port:dbg_port_inst|ci_uart:serial_port_inst|ci_fifo:receiver_fifo|ci_dp_ram_1c1r1w:memory_inst|altsyncram:ram_rtl_0|altsyncram_70o1:auto_generated|ALTSYNCRAM",
	mixed_port_feed_through_mode => "old",
	operation_mode => "dual_port",
	port_a_address_clear => "none",
	port_a_address_width => 4,
	port_a_byte_enable_clock => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "none",
	port_a_data_width => 36,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 15,
	port_a_logical_ram_depth => 16,
	port_a_logical_ram_width => 8,
	port_a_read_during_write_mode => "new_data_with_nbe_read",
	port_b_address_clear => "none",
	port_b_address_clock => "clock0",
	port_b_address_width => 4,
	port_b_data_out_clear => "none",
	port_b_data_out_clock => "none",
	port_b_data_width => 36,
	port_b_first_address => 0,
	port_b_first_bit_number => 0,
	port_b_last_address => 15,
	port_b_logical_ram_depth => 16,
	port_b_logical_ram_width => 8,
	port_b_read_during_write_mode => "new_data_with_nbe_read",
	port_b_read_enable_clock => "clock0",
	ram_block_type => "M9K")
-- pragma translate_on
PORT MAP (
	portawe => \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\,
	portbre => VCC,
	portbaddrstall => \dbg_port_inst|serial_port_inst|receiver_fifo|ALT_INV_rd_int~combout\,
	clk0 => \clk~inputclkctrl_outclk\,
	portadatain => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
	portaaddr => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
	portbaddr => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portbdataout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);

-- Location: LCCOMB_X50_Y47_N18
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~27\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~27_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~20_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~20_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~27_combout\);

-- Location: LCCOMB_X50_Y48_N10
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\);

-- Location: FF_X50_Y48_N11
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(22));

-- Location: LCCOMB_X50_Y47_N26
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~28\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~28_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(22) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(21))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~27_combout\))))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(22) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(21)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(21),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~27_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(22),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~28_combout\);

-- Location: FF_X50_Y47_N27
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~28_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6));

-- Location: FF_X49_Y47_N29
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[23]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(7),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(23));

-- Location: FF_X50_Y47_N5
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~21\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(7),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~21_q\);

-- Location: LCCOMB_X50_Y47_N4
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~29\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~29_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~21_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~21_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~29_combout\);

-- Location: LCCOMB_X50_Y48_N28
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\);

-- Location: FF_X50_Y48_N29
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[24]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(24));

-- Location: LCCOMB_X50_Y47_N20
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~30\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~30_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(23))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(24) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~29_combout\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(24) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(23)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(23),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~29_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(24),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~30_combout\);

-- Location: FF_X50_Y47_N21
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~30_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7));

-- Location: LCCOMB_X49_Y47_N8
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(5),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\);

-- Location: FF_X49_Y47_N9
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(19));

-- Location: LCCOMB_X50_Y48_N16
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\);

-- Location: FF_X50_Y48_N17
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(20));

-- Location: FF_X50_Y47_N7
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~19\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(5),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~19_q\);

-- Location: LCCOMB_X50_Y47_N6
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~22\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~22_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~19_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~19_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~22_combout\);

-- Location: LCCOMB_X50_Y47_N8
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~26\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~26_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(19))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(20) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~22_combout\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(20) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(19)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(19),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(20),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~22_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~26_combout\);

-- Location: FF_X50_Y47_N9
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~26_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5));

-- Location: LCCOMB_X48_Y44_N16
\dbg_port_inst|Mux0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Mux0~1_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7) & \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5),
	combout => \dbg_port_inst|Mux0~1_combout\);

-- Location: FF_X50_Y47_N15
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~14\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(0),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~14_q\);

-- Location: LCCOMB_X50_Y47_N14
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~39\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~39_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & 
-- ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~14_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~14_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~39_combout\);

-- Location: LCCOMB_X50_Y48_N12
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\);

-- Location: FF_X50_Y48_N13
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(10));

-- Location: LCCOMB_X49_Y47_N20
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[9]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\);

-- Location: FF_X49_Y47_N21
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(9));

-- Location: LCCOMB_X50_Y47_N12
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~40\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~40_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & (((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(9))))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(10) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~39_combout\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(10) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(9))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111101000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~39_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(10),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(9),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~40_combout\);

-- Location: FF_X50_Y47_N13
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~40_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0));

-- Location: FF_X50_Y47_N25
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~15\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(1),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~15_q\);

-- Location: LCCOMB_X50_Y47_N24
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~33\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~33_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~15_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~15_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~33_combout\);

-- Location: LCCOMB_X49_Y47_N16
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[11]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[11]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(1),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[11]~feeder_combout\);

-- Location: FF_X49_Y47_N17
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[11]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(11));

-- Location: LCCOMB_X50_Y48_N24
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\);

-- Location: FF_X50_Y48_N25
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(12));

-- Location: LCCOMB_X50_Y47_N16
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~34\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~34_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & (((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(11))))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(12) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~33_combout\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(12) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(11))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~33_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(11),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(12),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~34_combout\);

-- Location: FF_X50_Y47_N17
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~34_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1));

-- Location: FF_X50_Y47_N23
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~17\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(3),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~17_q\);

-- Location: LCCOMB_X50_Y47_N22
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~31\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~31_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~17_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~17_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~31_combout\);

-- Location: LCCOMB_X50_Y48_N30
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\);

-- Location: FF_X50_Y48_N31
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(16));

-- Location: FF_X49_Y47_N15
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(3),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(15));

-- Location: LCCOMB_X50_Y47_N30
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~32\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~32_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & (((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(15))))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(16) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~31_combout\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(16) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(15))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111100100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~31_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(16),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(15),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~32_combout\);

-- Location: FF_X50_Y47_N31
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~32_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3));

-- Location: FF_X50_Y47_N3
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~16\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(2),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~16_q\);

-- Location: LCCOMB_X50_Y47_N2
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~35\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~35_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~16_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~16_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~35_combout\);

-- Location: LCCOMB_X49_Y47_N26
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[13]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(2),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\);

-- Location: FF_X49_Y47_N27
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(13));

-- Location: LCCOMB_X50_Y48_N26
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\);

-- Location: FF_X50_Y48_N27
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(14));

-- Location: LCCOMB_X50_Y47_N10
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~36\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~36_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & (((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(13))))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(14) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~35_combout\)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(14) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(13))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~35_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(13),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(14),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~36_combout\);

-- Location: FF_X50_Y47_N11
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~36_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2));

-- Location: LCCOMB_X47_Y48_N6
\dbg_port_inst|Mux0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Mux0~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) & 
-- !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|Mux0~0_combout\);

-- Location: LCCOMB_X47_Y44_N22
\dbg_port_inst|Mux0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Mux0~2_combout\ = (\dbg_port_inst|Mux0~1_combout\ & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & \dbg_port_inst|Mux0~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|Mux0~1_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datad => \dbg_port_inst|Mux0~0_combout\,
	combout => \dbg_port_inst|Mux0~2_combout\);

-- Location: LCCOMB_X47_Y48_N28
\dbg_port_inst|hex_reader_inst|process_0~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~6_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & 
-- !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000001100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|process_0~6_combout\);

-- Location: LCCOMB_X48_Y44_N22
\dbg_port_inst|hex_reader_inst|process_0~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~7_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6) & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5),
	combout => \dbg_port_inst|hex_reader_inst|process_0~7_combout\);

-- Location: LCCOMB_X47_Y44_N0
\dbg_port_inst|hex_reader_inst|Selector7~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector7~1_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & ((!\dbg_port_inst|hex_reader_inst|process_0~7_combout\) # (!\dbg_port_inst|hex_reader_inst|process_0~6_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|process_0~6_combout\,
	datad => \dbg_port_inst|hex_reader_inst|process_0~7_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector7~1_combout\);

-- Location: LCCOMB_X48_Y44_N24
\dbg_port_inst|hex_reader_inst|process_0~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~8_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6) & \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5),
	combout => \dbg_port_inst|hex_reader_inst|process_0~8_combout\);

-- Location: LCCOMB_X48_Y44_N26
\dbg_port_inst|hex_reader_inst|process_0~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~9_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & (\dbg_port_inst|hex_reader_inst|process_0~8_combout\ & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datab => \dbg_port_inst|hex_reader_inst|process_0~8_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|process_0~9_combout\);

-- Location: LCCOMB_X47_Y44_N26
\dbg_port_inst|hex_reader_inst|Selector7~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector7~2_combout\ = (!\dbg_port_inst|Mux0~2_combout\ & (\dbg_port_inst|hex_reader_inst|Selector7~1_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4)) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~9_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Mux0~2_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Selector7~1_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datad => \dbg_port_inst|hex_reader_inst|process_0~9_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector7~2_combout\);

-- Location: LCCOMB_X48_Y44_N0
\dbg_port_inst|hex_reader_inst|process_0~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~4_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7) & 
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5),
	combout => \dbg_port_inst|hex_reader_inst|process_0~4_combout\);

-- Location: LCCOMB_X46_Y48_N22
\dbg_port_inst|Selector1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector1~0_combout\ = (!\dbg_port_inst|fsm_state~33_combout\ & (\dbg_port_inst|Selector0~0_combout\ & (!\dbg_port_inst|fsm_state.WAIT_READ~q\ & !\dbg_port_inst|fsm_state.READ_COMMAND~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state~33_combout\,
	datab => \dbg_port_inst|Selector0~0_combout\,
	datac => \dbg_port_inst|fsm_state.WAIT_READ~q\,
	datad => \dbg_port_inst|fsm_state.READ_COMMAND~q\,
	combout => \dbg_port_inst|Selector1~0_combout\);

-- Location: FF_X46_Y48_N23
\dbg_port_inst|fsm_state.WAIT_READ\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector1~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.WAIT_READ~q\);

-- Location: FF_X46_Y48_N15
\dbg_port_inst|fsm_state.READ_COMMAND\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|fsm_state.WAIT_READ~q\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.READ_COMMAND~q\);

-- Location: LCCOMB_X46_Y48_N4
\dbg_port_inst|Selector12~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector12~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & (\dbg_port_inst|Mux0~1_combout\ & \dbg_port_inst|fsm_state.READ_COMMAND~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datab => \dbg_port_inst|Mux0~1_combout\,
	datad => \dbg_port_inst|fsm_state.READ_COMMAND~q\,
	combout => \dbg_port_inst|Selector12~0_combout\);

-- Location: LCCOMB_X47_Y48_N30
\dbg_port_inst|Selector3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector3~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	combout => \dbg_port_inst|Selector3~0_combout\);

-- Location: LCCOMB_X47_Y48_N24
\dbg_port_inst|Selector3~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector3~1_combout\ = (\dbg_port_inst|fsm_state.READ_COMMAND~q\ & (\dbg_port_inst|Mux0~1_combout\ & (\dbg_port_inst|Selector3~0_combout\ & \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.READ_COMMAND~q\,
	datab => \dbg_port_inst|Mux0~1_combout\,
	datac => \dbg_port_inst|Selector3~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	combout => \dbg_port_inst|Selector3~1_combout\);

-- Location: LCCOMB_X47_Y48_N0
\dbg_port_inst|Selector7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector7~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & (\dbg_port_inst|Selector3~1_combout\ & \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datab => \dbg_port_inst|Selector3~1_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|Selector7~0_combout\);

-- Location: LCCOMB_X47_Y48_N18
\dbg_port_inst|Selector3~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector3~2_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & (\dbg_port_inst|Selector3~1_combout\ & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datab => \dbg_port_inst|Selector3~1_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|Selector3~2_combout\);

-- Location: FF_X47_Y48_N19
\dbg_port_inst|fsm_state.READ_OPERATION\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector3~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|Selector0~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.READ_OPERATION~q\);

-- Location: LCCOMB_X47_Y48_N10
\dbg_port_inst|hex_reader_inst|Add3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add3~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	combout => \dbg_port_inst|hex_reader_inst|Add3~0_combout\);

-- Location: LCCOMB_X48_Y44_N12
\dbg_port_inst|hex_reader_inst|process_0~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~17_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7)) # ((\dbg_port_inst|hex_reader_inst|process_0~5_combout\) # 
-- ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6)) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7),
	datab => \dbg_port_inst|hex_reader_inst|process_0~5_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(5),
	combout => \dbg_port_inst|hex_reader_inst|process_0~17_combout\);

-- Location: LCCOMB_X47_Y48_N14
\dbg_port_inst|hex_reader_inst|Selector31~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector31~0_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) $ (((\dbg_port_inst|hex_reader_inst|process_0~17_combout\ & 
-- ((!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)) # (!\dbg_port_inst|hex_reader_inst|Add3~0_combout\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011010000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|Add3~0_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~17_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|Selector31~0_combout\);

-- Location: LCCOMB_X47_Y44_N20
\dbg_port_inst|hex_reader_inst|process_0~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~10_combout\ = (\dbg_port_inst|hex_reader_inst|process_0~6_combout\ & ((\dbg_port_inst|hex_reader_inst|process_0~7_combout\) # ((\dbg_port_inst|hex_reader_inst|process_0~9_combout\ & 
-- !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4))))) # (!\dbg_port_inst|hex_reader_inst|process_0~6_combout\ & (\dbg_port_inst|hex_reader_inst|process_0~9_combout\ & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~6_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~9_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datad => \dbg_port_inst|hex_reader_inst|process_0~7_combout\,
	combout => \dbg_port_inst|hex_reader_inst|process_0~10_combout\);

-- Location: LCCOMB_X48_Y44_N28
\dbg_port_inst|hex_reader_inst|LessThan4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|LessThan4~0_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) & 
-- !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|LessThan4~0_combout\);

-- Location: LCCOMB_X48_Y44_N18
\dbg_port_inst|hex_reader_inst|process_0~16\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~16_combout\ = (\dbg_port_inst|hex_reader_inst|LessThan4~0_combout\ & (\dbg_port_inst|hex_reader_inst|process_0~8_combout\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & 
-- \dbg_port_inst|hex_reader_inst|first_char~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|LessThan4~0_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~8_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datad => \dbg_port_inst|hex_reader_inst|first_char~q\,
	combout => \dbg_port_inst|hex_reader_inst|process_0~16_combout\);

-- Location: LCCOMB_X47_Y44_N8
\dbg_port_inst|hex_reader_inst|value[1]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|value[1]~1_combout\ = ((\dbg_port_inst|Mux0~2_combout\) # (\dbg_port_inst|hex_reader_inst|process_0~16_combout\)) # (!\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|Mux0~2_combout\,
	datad => \dbg_port_inst|hex_reader_inst|process_0~16_combout\,
	combout => \dbg_port_inst|hex_reader_inst|value[1]~1_combout\);

-- Location: LCCOMB_X47_Y44_N2
\dbg_port_inst|hex_reader_inst|value[1]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|value[1]~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.IDLE~q\) # (!\dbg_port_inst|hex_reader_start~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_start~q\,
	datad => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	combout => \dbg_port_inst|hex_reader_inst|value[1]~0_combout\);

-- Location: LCCOMB_X47_Y44_N10
\dbg_port_inst|hex_reader_inst|value[1]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|value[1]~2_combout\ = ((!\dbg_port_inst|hex_reader_inst|state~22_combout\ & (!\dbg_port_inst|hex_reader_inst|process_0~10_combout\ & !\dbg_port_inst|hex_reader_inst|value[1]~1_combout\))) # 
-- (!\dbg_port_inst|hex_reader_inst|value[1]~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state~22_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~10_combout\,
	datac => \dbg_port_inst|hex_reader_inst|value[1]~1_combout\,
	datad => \dbg_port_inst|hex_reader_inst|value[1]~0_combout\,
	combout => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\);

-- Location: FF_X47_Y48_N15
\dbg_port_inst|hex_reader_inst|value[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector31~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(3));

-- Location: LCCOMB_X47_Y48_N12
\dbg_port_inst|hex_reader_inst|Selector32~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector32~0_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2) $ (((\dbg_port_inst|hex_reader_inst|Add3~0_combout\ & ((\dbg_port_inst|hex_reader_inst|process_0~5_combout\) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~4_combout\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010111111010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~5_combout\,
	datac => \dbg_port_inst|hex_reader_inst|Add3~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|Selector32~0_combout\);

-- Location: FF_X47_Y48_N13
\dbg_port_inst|hex_reader_inst|value[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector32~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(2));

-- Location: LCCOMB_X47_Y48_N26
\dbg_port_inst|hex_reader_inst|Selector33~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector33~0_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) $ (((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & 
-- ((\dbg_port_inst|hex_reader_inst|process_0~5_combout\) # (!\dbg_port_inst|hex_reader_inst|process_0~4_combout\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011100111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~4_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|hex_reader_inst|process_0~5_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	combout => \dbg_port_inst|hex_reader_inst|Selector33~0_combout\);

-- Location: FF_X47_Y48_N27
\dbg_port_inst|hex_reader_inst|value[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector33~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(1));

-- Location: LCCOMB_X47_Y48_N8
\dbg_port_inst|hex_reader_inst|Selector34~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector34~0_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) $ (((\dbg_port_inst|hex_reader_inst|process_0~5_combout\) # (!\dbg_port_inst|hex_reader_inst|process_0~4_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001011011101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~5_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	combout => \dbg_port_inst|hex_reader_inst|Selector34~0_combout\);

-- Location: FF_X47_Y48_N9
\dbg_port_inst|hex_reader_inst|value[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector34~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(0));

-- Location: LCCOMB_X42_Y48_N4
\dbg_port_inst|hex_writer_value~75\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~75_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & ((\dbg_port_inst|hex_reader_inst|value\(2) & ((\dbg_port_inst|hex_reader_inst|value\(1)) # (\dbg_port_inst|hex_reader_inst|value\(0)))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(2) & ((!\dbg_port_inst|hex_reader_inst|value\(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100010100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|hex_writer_value~75_combout\);

-- Location: LCCOMB_X42_Y48_N16
\dbg_port_inst|Selector6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector6~0_combout\ = (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & (!\dbg_port_inst|hex_writer_value~75_combout\ & \dbg_port_inst|hex_reader_inst|done~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datab => \dbg_port_inst|hex_writer_value~75_combout\,
	datac => \dbg_port_inst|hex_reader_inst|done~q\,
	combout => \dbg_port_inst|Selector6~0_combout\);

-- Location: LCCOMB_X41_Y48_N2
\dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\) # ((\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\) # ((\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\) # 
-- (\dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~0_combout\);

-- Location: LCCOMB_X41_Y48_N10
\dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~1_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~0_combout\ & !\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~0_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~1_combout\);

-- Location: LCCOMB_X41_Y48_N0
\dbg_port_inst|ci_hex_writer_inst|state.IDLE~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.IDLE~5_combout\ = !\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~5_combout\);

-- Location: LCCOMB_X40_Y48_N18
\dbg_port_inst|hex_writer_width~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width~8_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(2)) # (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_width~8_combout\);

-- Location: LCCOMB_X40_Y48_N30
\dbg_port_inst|hex_reader_inst|value[2]~_wirecell\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|value[2]~_wirecell_combout\ = !\dbg_port_inst|hex_reader_inst|value\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_reader_inst|value[2]~_wirecell_combout\);

-- Location: LCCOMB_X40_Y48_N24
\dbg_port_inst|hex_writer_width[5]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width[5]~5_combout\ = ((\dbg_port_inst|hex_reader_inst|value\(2) & (!\dbg_port_inst|hex_reader_inst|value\(0) & !\dbg_port_inst|hex_reader_inst|value\(1))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & 
-- (\dbg_port_inst|hex_reader_inst|value\(0)))) # (!\dbg_port_inst|hex_reader_inst|value\(3))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111001101111011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(3),
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_width[5]~5_combout\);

-- Location: LCCOMB_X40_Y48_N8
\dbg_port_inst|hex_writer_width[5]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width[5]~9_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & (\res_n~input_o\ & (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & \dbg_port_inst|hex_writer_width[5]~5_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datab => \res_n~input_o\,
	datac => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datad => \dbg_port_inst|hex_writer_width[5]~5_combout\,
	combout => \dbg_port_inst|hex_writer_width[5]~9_combout\);

-- Location: FF_X40_Y48_N19
\dbg_port_inst|hex_writer_width[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_width~8_combout\,
	asdata => \dbg_port_inst|hex_reader_inst|value[2]~_wirecell_combout\,
	sload => \dbg_port_inst|hex_reader_inst|value\(3),
	ena => \dbg_port_inst|hex_writer_width[5]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_width\(0));

-- Location: LCCOMB_X42_Y46_N0
\dbg_port_inst|hex_writer_value~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~15_combout\ = (\dbg_port_inst|hex_reader_inst|value\(1) & !\dbg_port_inst|hex_reader_inst|value\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_writer_value~15_combout\);

-- Location: FF_X42_Y46_N1
\dbg_port_inst|hex_writer_width[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~15_combout\,
	asdata => \~GND~combout\,
	sclr => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => \dbg_port_inst|hex_reader_inst|ALT_INV_value\(0),
	ena => \dbg_port_inst|hex_writer_width[5]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_width\(2));

-- Location: LCCOMB_X42_Y47_N16
\dbg_port_inst|hex_writer_width~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width~4_combout\ = \dbg_port_inst|hex_reader_inst|value\(1) $ (\dbg_port_inst|hex_reader_inst|value\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_writer_width~4_combout\);

-- Location: FF_X42_Y47_N17
\dbg_port_inst|hex_writer_width[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_width~4_combout\,
	asdata => \~GND~combout\,
	sclr => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => \dbg_port_inst|hex_reader_inst|value\(0),
	ena => \dbg_port_inst|hex_writer_width[5]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_width\(1));

-- Location: LCCOMB_X41_Y47_N16
\dbg_port_inst|ci_hex_writer_inst|Selector71~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector71~0_combout\ = \dbg_port_inst|hex_writer_width\(2) $ (((\dbg_port_inst|hex_writer_width\(0)) # (\dbg_port_inst|hex_writer_width\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001101100110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_width\(0),
	datab => \dbg_port_inst|hex_writer_width\(2),
	datad => \dbg_port_inst|hex_writer_width\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector71~0_combout\);

-- Location: FF_X42_Y48_N17
\dbg_port_inst|hex_writer_start\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector6~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_start~q\);

-- Location: LCCOMB_X41_Y48_N28
\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\) # (!\dbg_port_inst|hex_writer_start~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|hex_writer_start~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\);

-- Location: LCCOMB_X41_Y48_N26
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx~7_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ & 
-- !\dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx~7_combout\);

-- Location: LCCOMB_X40_Y48_N16
\dbg_port_inst|hex_writer_width~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width~7_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & (\dbg_port_inst|hex_reader_inst|value\(2) & !\dbg_port_inst|hex_reader_inst|value\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(2),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_width~7_combout\);

-- Location: FF_X40_Y48_N17
\dbg_port_inst|hex_writer_width[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_width~7_combout\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	sload => \dbg_port_inst|hex_reader_inst|value\(3),
	ena => \dbg_port_inst|hex_writer_width[5]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_width\(3));

-- Location: LCCOMB_X41_Y47_N30
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~9_combout\ = \dbg_port_inst|hex_writer_width\(3) $ (((!\dbg_port_inst|hex_writer_width\(0) & (!\dbg_port_inst|hex_writer_width\(2) & !\dbg_port_inst|hex_writer_width\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_width\(0),
	datab => \dbg_port_inst|hex_writer_width\(2),
	datac => \dbg_port_inst|hex_writer_width\(3),
	datad => \dbg_port_inst|hex_writer_width\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~9_combout\);

-- Location: LCCOMB_X42_Y47_N26
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~10_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1) $ (((!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0)))))) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (((\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~9_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100001110100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1),
	datab => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~9_combout\,
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0),
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~10_combout\);

-- Location: LCCOMB_X42_Y47_N6
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~11_combout\ = (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ & ((\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1)))) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ & (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~10_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~10_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1),
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~11_combout\);

-- Location: FF_X42_Y47_N7
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[1]~11_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1));

-- Location: LCCOMB_X41_Y47_N24
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~4_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2) $ (((!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1) & 
-- !\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000010010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1),
	datab => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2),
	datac => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0),
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~4_combout\);

-- Location: LCCOMB_X41_Y47_N18
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~5_combout\ = (\dbg_port_inst|hex_writer_width\(1)) # ((!\dbg_port_inst|hex_writer_width\(0) & (!\dbg_port_inst|hex_writer_width\(2) & !\dbg_port_inst|hex_writer_width\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_width\(0),
	datab => \dbg_port_inst|hex_writer_width\(2),
	datac => \dbg_port_inst|hex_writer_width\(3),
	datad => \dbg_port_inst|hex_writer_width\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~5_combout\);

-- Location: LCCOMB_X41_Y47_N20
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~6_combout\ = (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~4_combout\) # ((!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~5_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~4_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~5_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~6_combout\);

-- Location: LCCOMB_X41_Y47_N2
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~8_combout\ = (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx~7_combout\ & (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~6_combout\)) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx~7_combout\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\ & ((\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2)))) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\ & (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~6_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx~7_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~6_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2),
	datad => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~8_combout\);

-- Location: FF_X41_Y47_N3
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[2]~8_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2));

-- Location: LCCOMB_X41_Y47_N14
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~1_combout\ = (\dbg_port_inst|hex_writer_width\(0)) # ((\dbg_port_inst|hex_writer_width\(2)) # ((\dbg_port_inst|hex_writer_width\(3)) # (\dbg_port_inst|hex_writer_width\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_width\(0),
	datab => \dbg_port_inst|hex_writer_width\(2),
	datac => \dbg_port_inst|hex_writer_width\(3),
	datad => \dbg_port_inst|hex_writer_width\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~1_combout\);

-- Location: LCCOMB_X42_Y47_N14
\dbg_port_inst|ci_hex_writer_inst|Add3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Add3~0_combout\ = \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3) $ (((\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2)) # ((\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0)) # 
-- (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100011110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2),
	datab => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0),
	datac => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3),
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|Add3~0_combout\);

-- Location: LCCOMB_X42_Y47_N10
\dbg_port_inst|hex_writer_width~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width~6_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(1) & !\dbg_port_inst|hex_reader_inst|value\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_writer_width~6_combout\);

-- Location: FF_X42_Y47_N11
\dbg_port_inst|hex_writer_width[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_width~6_combout\,
	asdata => \~GND~combout\,
	sclr => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => \dbg_port_inst|hex_reader_inst|value\(0),
	ena => \dbg_port_inst|hex_writer_width[5]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_width\(5));

-- Location: LCCOMB_X42_Y47_N0
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~2_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (((\dbg_port_inst|ci_hex_writer_inst|Add3~0_combout\)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & 
-- (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~1_combout\ $ (((\dbg_port_inst|hex_writer_width\(5))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101000111100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~1_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|Add3~0_combout\,
	datad => \dbg_port_inst|hex_writer_width\(5),
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~2_combout\);

-- Location: LCCOMB_X42_Y47_N4
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~3_combout\ = (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ & ((\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3)))) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ & (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~2_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~2_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3),
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~3_combout\);

-- Location: FF_X42_Y47_N5
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3));

-- Location: LCCOMB_X42_Y47_N2
\dbg_port_inst|ci_hex_writer_inst|Equal2~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2) & (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0) & (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3) & 
-- !\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2),
	datab => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0),
	datac => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3),
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\);

-- Location: LCCOMB_X42_Y47_N28
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\) # ((\dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\) 
-- # (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100100011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~2_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\);

-- Location: LCCOMB_X42_Y47_N24
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[0]~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[0]~12_combout\ = (\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ & (((\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0))))) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\ & ((\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & ((!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & 
-- (!\dbg_port_inst|ci_hex_writer_inst|Selector71~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000011101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|Selector71~0_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0),
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[3]~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[0]~12_combout\);

-- Location: FF_X42_Y47_N25
\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx[0]~12_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0));

-- Location: LCCOMB_X41_Y47_N22
\dbg_port_inst|ci_hex_writer_inst|shift_amount[0]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|shift_amount[0]~3_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & (!\dbg_port_inst|ci_hex_writer_inst|shift_amount\(0))) # (!\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & 
-- ((!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(0),
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(0),
	combout => \dbg_port_inst|ci_hex_writer_inst|shift_amount[0]~3_combout\);

-- Location: LCCOMB_X41_Y48_N30
\dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\)) # (!\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & 
-- ((!\dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4_combout\);

-- Location: FF_X41_Y47_N23
\dbg_port_inst|ci_hex_writer_inst|shift_amount[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|shift_amount[0]~3_combout\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(0),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(0));

-- Location: LCCOMB_X41_Y47_N6
\dbg_port_inst|ci_hex_writer_inst|Add1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Add1~2_combout\ = \dbg_port_inst|ci_hex_writer_inst|shift_amount\(1) $ (\dbg_port_inst|ci_hex_writer_inst|shift_amount\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(1),
	datac => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(0),
	combout => \dbg_port_inst|ci_hex_writer_inst|Add1~2_combout\);

-- Location: LCCOMB_X41_Y47_N28
\dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~2_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & (!\dbg_port_inst|ci_hex_writer_inst|Add1~2_combout\)) # (!\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & 
-- ((!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100010001110111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|Add1~2_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~2_combout\);

-- Location: FF_X41_Y47_N29
\dbg_port_inst|ci_hex_writer_inst|shift_amount[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~2_combout\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(1),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(1));

-- Location: LCCOMB_X41_Y47_N12
\dbg_port_inst|ci_hex_writer_inst|Add1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Add1~1_combout\ = \dbg_port_inst|ci_hex_writer_inst|shift_amount\(2) $ (((\dbg_port_inst|ci_hex_writer_inst|shift_amount\(1)) # (\dbg_port_inst|ci_hex_writer_inst|shift_amount\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101011001010110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(2),
	datab => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(1),
	datac => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(0),
	combout => \dbg_port_inst|ci_hex_writer_inst|Add1~1_combout\);

-- Location: LCCOMB_X41_Y47_N26
\dbg_port_inst|ci_hex_writer_inst|shift_amount[2]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|shift_amount[2]~1_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & (!\dbg_port_inst|ci_hex_writer_inst|Add1~1_combout\)) # (!\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & 
-- ((!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100010001110111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|Add1~1_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(2),
	combout => \dbg_port_inst|ci_hex_writer_inst|shift_amount[2]~1_combout\);

-- Location: FF_X41_Y47_N27
\dbg_port_inst|ci_hex_writer_inst|shift_amount[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|shift_amount[2]~1_combout\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(2),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(2));

-- Location: LCCOMB_X41_Y47_N10
\dbg_port_inst|ci_hex_writer_inst|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Add1~0_combout\ = \dbg_port_inst|ci_hex_writer_inst|shift_amount\(3) $ (((\dbg_port_inst|ci_hex_writer_inst|shift_amount\(0)) # ((\dbg_port_inst|ci_hex_writer_inst|shift_amount\(1)) # 
-- (\dbg_port_inst|ci_hex_writer_inst|shift_amount\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(0),
	datab => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(1),
	datac => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(2),
	datad => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(3),
	combout => \dbg_port_inst|ci_hex_writer_inst|Add1~0_combout\);

-- Location: LCCOMB_X41_Y47_N0
\dbg_port_inst|ci_hex_writer_inst|shift_amount[3]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|shift_amount[3]~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & (!\dbg_port_inst|ci_hex_writer_inst|Add1~0_combout\)) # (!\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & 
-- ((!\dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100010001110111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|Add1~0_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|last_hex_digit_idx\(3),
	combout => \dbg_port_inst|ci_hex_writer_inst|shift_amount[3]~0_combout\);

-- Location: FF_X41_Y47_N1
\dbg_port_inst|ci_hex_writer_inst|shift_amount[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|shift_amount[3]~0_combout\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(3),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => \dbg_port_inst|ci_hex_writer_inst|shift_amount[1]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(3));

-- Location: LCCOMB_X41_Y47_N4
\dbg_port_inst|ci_hex_writer_inst|state.IDLE~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|shift_amount\(2) & (!\dbg_port_inst|ci_hex_writer_inst|shift_amount\(1) & (!\dbg_port_inst|ci_hex_writer_inst|shift_amount\(0) & 
-- !\dbg_port_inst|ci_hex_writer_inst|shift_amount\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(2),
	datab => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(1),
	datac => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(0),
	datad => \dbg_port_inst|ci_hex_writer_inst|shift_amount\(3),
	combout => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\);

-- Location: LCCOMB_X41_Y48_N12
\dbg_port_inst|ci_hex_writer_inst|state.IDLE~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.IDLE~3_combout\ = ((!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\ & \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\)) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~3_combout\);

-- Location: LCCOMB_X41_Y48_N14
\dbg_port_inst|ci_hex_writer_inst|state.IDLE~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.IDLE~1_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\ & (!\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\) # 
-- (!\dbg_port_inst|hex_writer_start~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010000000101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\,
	datad => \dbg_port_inst|hex_writer_start~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~1_combout\);

-- Location: LCCOMB_X41_Y48_N18
\dbg_port_inst|ci_hex_writer_inst|state.IDLE~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.IDLE~2_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\) # ((!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\ & 
-- !\dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000001101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~2_combout\);

-- Location: LCCOMB_X41_Y48_N6
\dbg_port_inst|ci_hex_writer_inst|state.IDLE~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.IDLE~4_combout\ = (\res_n~input_o\ & (((!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~3_combout\ & !\dbg_port_inst|ci_hex_writer_inst|state.IDLE~2_combout\)) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~1_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000001110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~3_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~1_combout\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~2_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~4_combout\);

-- Location: FF_X41_Y48_N1
\dbg_port_inst|ci_hex_writer_inst|state.IDLE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~5_combout\,
	ena => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\);

-- Location: LCCOMB_X41_Y48_N20
\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~1_combout\ = ((\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ & ((\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\) # (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\)))) # 
-- (!\res_n~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100100011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	datad => \res_n~input_o\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~1_combout\);

-- Location: LCCOMB_X41_Y48_N22
\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\ & (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & ((!\dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\)))) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\ & ((\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\) # ((\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & !\dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000011011100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|Equal2~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~0_combout\);

-- Location: LCCOMB_X41_Y48_N16
\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~1_combout\ & (!\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~0_combout\ & ((\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\) # 
-- (\dbg_port_inst|hex_writer_start~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~1_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~0_combout\,
	datad => \dbg_port_inst|hex_writer_start~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2_combout\);

-- Location: FF_X41_Y48_N11
\dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~1_combout\,
	ena => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\);

-- Location: FF_X41_Y48_N19
\dbg_port_inst|ci_hex_writer_inst|state.SHIFT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|state.CALC_SHIFT~q\,
	sload => VCC,
	ena => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\);

-- Location: FF_X41_Y48_N29
\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	sload => VCC,
	ena => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\);

-- Location: FF_X41_Y48_N21
\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	sload => VCC,
	ena => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\);

-- Location: FF_X41_Y48_N15
\dbg_port_inst|ci_hex_writer_inst|state.COMPLETE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	sload => VCC,
	ena => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\);

-- Location: FF_X46_Y48_N7
\dbg_port_inst|ci_hex_writer_inst|done\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|state.COMPLETE~q\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|done~q\);

-- Location: LCCOMB_X46_Y48_N0
\dbg_port_inst|Selector6~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector6~1_combout\ = (\dbg_port_inst|Selector6~0_combout\) # ((\dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\ & !\dbg_port_inst|ci_hex_writer_inst|done~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|Selector6~0_combout\,
	datac => \dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|done~q\,
	combout => \dbg_port_inst|Selector6~1_combout\);

-- Location: FF_X46_Y48_N1
\dbg_port_inst|fsm_state.WAIT_HEX_WRITER\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector6~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\);

-- Location: LCCOMB_X46_Y48_N8
\dbg_port_inst|hex_reader_inst|Selector5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector5~0_combout\ = (\dbg_port_inst|Mux0~0_combout\ & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & (\dbg_port_inst|Mux0~1_combout\ & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Mux0~0_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datac => \dbg_port_inst|Mux0~1_combout\,
	datad => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector5~0_combout\);

-- Location: FF_X46_Y48_N9
\dbg_port_inst|hex_reader_inst|state.COMPLETE_ABORT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector5~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|state.COMPLETE_ABORT~q\);

-- Location: FF_X46_Y48_N5
\dbg_port_inst|hex_reader_inst|abort\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|state.COMPLETE_ABORT~q\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|abort~q\);

-- Location: LCCOMB_X45_Y48_N28
\dbg_port_inst|Selector9~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~7_combout\ = (!\dbg_port_inst|hex_reader_inst|done~q\ & ((\dbg_port_inst|hex_reader_inst|parse_error~q\) # ((\dbg_port_inst|fsm_state.PRINT_ERROR~q\ & !\dbg_port_inst|hex_reader_inst|abort~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datab => \dbg_port_inst|fsm_state.PRINT_ERROR~q\,
	datac => \dbg_port_inst|hex_reader_inst|parse_error~q\,
	datad => \dbg_port_inst|hex_reader_inst|abort~q\,
	combout => \dbg_port_inst|Selector9~7_combout\);

-- Location: LCCOMB_X42_Y48_N2
\dbg_port_inst|write_address[3]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|write_address[3]~0_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|done~q\,
	datad => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	combout => \dbg_port_inst|write_address[3]~0_combout\);

-- Location: FF_X45_Y48_N11
\dbg_port_inst|write_address[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|write_address[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|write_address\(3));

-- Location: FF_X45_Y48_N17
\dbg_port_inst|write_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|write_address[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|write_address\(1));

-- Location: FF_X45_Y48_N1
\dbg_port_inst|write_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|write_address[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|write_address\(0));

-- Location: FF_X45_Y48_N19
\dbg_port_inst|write_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|write_address[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|write_address\(2));

-- Location: LCCOMB_X45_Y48_N0
\dbg_port_inst|fsm_state~32\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|fsm_state~32_combout\ = (\dbg_port_inst|write_address\(1) & ((\dbg_port_inst|write_address\(0) & (\dbg_port_inst|write_address\(3))) # (!\dbg_port_inst|write_address\(0) & ((\dbg_port_inst|write_address\(2)))))) # 
-- (!\dbg_port_inst|write_address\(1) & (((\dbg_port_inst|write_address\(0))) # (!\dbg_port_inst|write_address\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011110110110001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|write_address\(3),
	datab => \dbg_port_inst|write_address\(1),
	datac => \dbg_port_inst|write_address\(0),
	datad => \dbg_port_inst|write_address\(2),
	combout => \dbg_port_inst|fsm_state~32_combout\);

-- Location: LCCOMB_X42_Y48_N6
\dbg_port_inst|Selector9~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~3_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & ((\dbg_port_inst|hex_reader_inst|value\(2)) # ((\dbg_port_inst|hex_reader_inst|value\(0))))) # (!\dbg_port_inst|hex_reader_inst|value\(3) & 
-- (((\dbg_port_inst|hex_reader_inst|value\(2) & !\dbg_port_inst|hex_reader_inst|value\(0))) # (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111111001101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|Selector9~3_combout\);

-- Location: LCCOMB_X42_Y48_N10
\dbg_port_inst|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Equal0~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & (\dbg_port_inst|hex_reader_inst|value\(2) & (!\dbg_port_inst|hex_reader_inst|value\(1) & !\dbg_port_inst|hex_reader_inst|value\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|Equal0~0_combout\);

-- Location: LCCOMB_X42_Y48_N28
\dbg_port_inst|Selector9~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~2_combout\ = (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & ((\dbg_port_inst|hex_reader_inst|value\(0) & (\dbg_port_inst|hex_reader_inst|value\(2))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & 
-- ((!\dbg_port_inst|Equal0~0_combout\) # (!\dbg_port_inst|hex_reader_inst|value\(2))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001000011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(0),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datad => \dbg_port_inst|Equal0~0_combout\,
	combout => \dbg_port_inst|Selector9~2_combout\);

-- Location: LCCOMB_X42_Y48_N8
\dbg_port_inst|Selector9~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~4_combout\ = (\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\ & !\dbg_port_inst|Equal0~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	datad => \dbg_port_inst|Equal0~0_combout\,
	combout => \dbg_port_inst|Selector9~4_combout\);

-- Location: LCCOMB_X42_Y48_N18
\dbg_port_inst|Selector9~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~5_combout\ = (\dbg_port_inst|Selector9~3_combout\ & ((\dbg_port_inst|Selector9~4_combout\) # ((\dbg_port_inst|Selector9~2_combout\ & \dbg_port_inst|hex_reader_inst|value\(3))))) # (!\dbg_port_inst|Selector9~3_combout\ & 
-- (\dbg_port_inst|Selector9~2_combout\ & ((\dbg_port_inst|hex_reader_inst|value\(3)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110110010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Selector9~3_combout\,
	datab => \dbg_port_inst|Selector9~2_combout\,
	datac => \dbg_port_inst|Selector9~4_combout\,
	datad => \dbg_port_inst|hex_reader_inst|value\(3),
	combout => \dbg_port_inst|Selector9~5_combout\);

-- Location: LCCOMB_X45_Y48_N6
\dbg_port_inst|Selector8~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector8~1_combout\ = (\dbg_port_inst|Selector8~0_combout\) # ((!\dbg_port_inst|fsm_state~31_combout\ & (\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\ & !\dbg_port_inst|hex_reader_inst|abort~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011011100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state~31_combout\,
	datab => \dbg_port_inst|Selector8~0_combout\,
	datac => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\,
	datad => \dbg_port_inst|hex_reader_inst|abort~q\,
	combout => \dbg_port_inst|Selector8~1_combout\);

-- Location: FF_X45_Y48_N7
\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector8~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\);

-- Location: LCCOMB_X45_Y48_N20
\dbg_port_inst|Selector9~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~6_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & ((\dbg_port_inst|Selector9~5_combout\) # ((\dbg_port_inst|fsm_state~32_combout\ & \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state~32_combout\,
	datab => \dbg_port_inst|Selector9~5_combout\,
	datac => \dbg_port_inst|hex_reader_inst|done~q\,
	datad => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\,
	combout => \dbg_port_inst|Selector9~6_combout\);

-- Location: LCCOMB_X47_Y48_N4
\dbg_port_inst|Mux4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Mux4~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) $ 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|Mux4~0_combout\);

-- Location: LCCOMB_X46_Y48_N10
\dbg_port_inst|Selector9~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~0_combout\ = ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & ((!\dbg_port_inst|Mux4~0_combout\))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & 
-- (!\dbg_port_inst|Mux0~0_combout\))) # (!\dbg_port_inst|Mux0~1_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001111111011111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Mux0~0_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datac => \dbg_port_inst|Mux0~1_combout\,
	datad => \dbg_port_inst|Mux4~0_combout\,
	combout => \dbg_port_inst|Selector9~0_combout\);

-- Location: LCCOMB_X46_Y48_N12
\dbg_port_inst|Selector9~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~1_combout\ = (\dbg_port_inst|Selector9~0_combout\ & \dbg_port_inst|fsm_state.READ_COMMAND~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Selector9~0_combout\,
	datad => \dbg_port_inst|fsm_state.READ_COMMAND~q\,
	combout => \dbg_port_inst|Selector9~1_combout\);

-- Location: LCCOMB_X45_Y48_N2
\dbg_port_inst|Selector0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~2_combout\ = (\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\) # ((\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\) # (\dbg_port_inst|fsm_state.READ_OPERATION~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\,
	datac => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	datad => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	combout => \dbg_port_inst|Selector0~2_combout\);

-- Location: LCCOMB_X45_Y48_N22
\dbg_port_inst|Selector9~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector9~8_combout\ = (\dbg_port_inst|Selector9~6_combout\) # ((\dbg_port_inst|Selector9~1_combout\) # ((\dbg_port_inst|Selector9~7_combout\ & \dbg_port_inst|Selector0~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Selector9~7_combout\,
	datab => \dbg_port_inst|Selector9~6_combout\,
	datac => \dbg_port_inst|Selector9~1_combout\,
	datad => \dbg_port_inst|Selector0~2_combout\,
	combout => \dbg_port_inst|Selector9~8_combout\);

-- Location: FF_X45_Y48_N23
\dbg_port_inst|fsm_state.PRINT_ERROR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector9~8_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.PRINT_ERROR~q\);

-- Location: LCCOMB_X46_Y48_N14
\dbg_port_inst|Selector0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~1_combout\ = (!\dbg_port_inst|fsm_state.PRINT_OK~q\ & (!\dbg_port_inst|fsm_state.WAIT_READ~q\ & (!\dbg_port_inst|fsm_state.READ_COMMAND~q\ & !\dbg_port_inst|fsm_state.PRINT_ERROR~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.PRINT_OK~q\,
	datab => \dbg_port_inst|fsm_state.WAIT_READ~q\,
	datac => \dbg_port_inst|fsm_state.READ_COMMAND~q\,
	datad => \dbg_port_inst|fsm_state.PRINT_ERROR~q\,
	combout => \dbg_port_inst|Selector0~1_combout\);

-- Location: LCCOMB_X46_Y48_N18
\dbg_port_inst|Selector0~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~3_combout\ = (!\dbg_port_inst|Selector0~0_combout\ & (\dbg_port_inst|Selector0~1_combout\ & ((!\dbg_port_inst|Selector0~2_combout\) # (!\dbg_port_inst|fsm_state~31_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state~31_combout\,
	datab => \dbg_port_inst|Selector0~0_combout\,
	datac => \dbg_port_inst|Selector0~1_combout\,
	datad => \dbg_port_inst|Selector0~2_combout\,
	combout => \dbg_port_inst|Selector0~3_combout\);

-- Location: LCCOMB_X46_Y48_N6
\dbg_port_inst|Selector0~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~6_combout\ = ((\dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\ & ((\dbg_port_inst|ci_hex_writer_inst|done~q\))) # (!\dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\ & (\dbg_port_inst|Selector0~5_combout\))) # 
-- (!\dbg_port_inst|Selector0~3_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110001011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Selector0~5_combout\,
	datab => \dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|done~q\,
	datad => \dbg_port_inst|Selector0~3_combout\,
	combout => \dbg_port_inst|Selector0~6_combout\);

-- Location: FF_X47_Y48_N1
\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector7~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|Selector0~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\);

-- Location: LCCOMB_X42_Y48_N12
\dbg_port_inst|fsm_state~30\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|fsm_state~30_combout\ = (\dbg_port_inst|hex_reader_inst|value\(1) & ((\dbg_port_inst|hex_reader_inst|value\(0) & (!\dbg_port_inst|hex_reader_inst|value\(3))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & 
-- ((!\dbg_port_inst|hex_reader_inst|value\(2)))))) # (!\dbg_port_inst|hex_reader_inst|value\(1) & (\dbg_port_inst|hex_reader_inst|value\(3) & ((!\dbg_port_inst|hex_reader_inst|value\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000000111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|fsm_state~30_combout\);

-- Location: LCCOMB_X42_Y48_N22
\dbg_port_inst|Selector8~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector8~0_combout\ = (\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\ & (\dbg_port_inst|hex_reader_inst|done~q\ & \dbg_port_inst|fsm_state~30_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	datac => \dbg_port_inst|hex_reader_inst|done~q\,
	datad => \dbg_port_inst|fsm_state~30_combout\,
	combout => \dbg_port_inst|Selector8~0_combout\);

-- Location: LCCOMB_X46_Y48_N2
\dbg_port_inst|Selector12~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector12~1_combout\ = (\dbg_port_inst|Selector8~0_combout\) # ((\dbg_port_inst|Selector12~0_combout\ & \dbg_port_inst|Mux4~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|Selector12~0_combout\,
	datac => \dbg_port_inst|Selector8~0_combout\,
	datad => \dbg_port_inst|Mux4~0_combout\,
	combout => \dbg_port_inst|Selector12~1_combout\);

-- Location: FF_X46_Y48_N3
\dbg_port_inst|hex_reader_start\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector12~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_start~q\);

-- Location: LCCOMB_X47_Y44_N16
\dbg_port_inst|hex_reader_inst|Selector0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector0~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.COMPLETE_DONE~q\) # ((\dbg_port_inst|hex_reader_inst|state.COMPLETE_ABORT~q\) # ((!\dbg_port_inst|hex_reader_start~q\ & 
-- !\dbg_port_inst|hex_reader_inst|state.IDLE~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011111101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_start~q\,
	datab => \dbg_port_inst|hex_reader_inst|state.COMPLETE_DONE~q\,
	datac => \dbg_port_inst|hex_reader_inst|state.COMPLETE_ABORT~q\,
	datad => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector0~0_combout\);

-- Location: LCCOMB_X47_Y44_N24
\dbg_port_inst|hex_reader_inst|Selector0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector0~1_combout\ = (!\dbg_port_inst|hex_reader_inst|state.COMPLETE_ERROR~q\ & !\dbg_port_inst|hex_reader_inst|Selector0~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|state.COMPLETE_ERROR~q\,
	datad => \dbg_port_inst|hex_reader_inst|Selector0~0_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector0~1_combout\);

-- Location: FF_X47_Y44_N25
\dbg_port_inst|hex_reader_inst|state.IDLE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|state.IDLE~q\);

-- Location: LCCOMB_X47_Y44_N18
\dbg_port_inst|hex_reader_inst|first_char~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|first_char~0_combout\ = (\dbg_port_inst|hex_reader_start~q\ & (\res_n~input_o\ & !\dbg_port_inst|hex_reader_inst|state.IDLE~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_start~q\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	combout => \dbg_port_inst|hex_reader_inst|first_char~0_combout\);

-- Location: LCCOMB_X47_Y44_N12
\dbg_port_inst|hex_reader_inst|expect_leading_space~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|expect_leading_space~2_combout\ = (!\dbg_port_inst|hex_reader_inst|state~22_combout\ & (!\dbg_port_inst|hex_reader_inst|process_0~10_combout\ & (!\dbg_port_inst|Mux0~2_combout\ & 
-- \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state~22_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~10_combout\,
	datac => \dbg_port_inst|Mux0~2_combout\,
	datad => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|expect_leading_space~2_combout\);

-- Location: LCCOMB_X48_Y44_N2
\dbg_port_inst|hex_reader_inst|first_char~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|first_char~1_combout\ = (\dbg_port_inst|hex_reader_inst|expect_leading_space~2_combout\ & (\res_n~input_o\ & !\dbg_port_inst|hex_reader_inst|process_0~16_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|expect_leading_space~2_combout\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|hex_reader_inst|process_0~16_combout\,
	combout => \dbg_port_inst|hex_reader_inst|first_char~1_combout\);

-- Location: LCCOMB_X49_Y44_N24
\dbg_port_inst|hex_reader_inst|first_char~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|first_char~2_combout\ = (\dbg_port_inst|hex_reader_inst|first_char~0_combout\ & (!\dbg_port_inst|hex_reader_inst|state.IDLE~q\)) # (!\dbg_port_inst|hex_reader_inst|first_char~0_combout\ & 
-- (\dbg_port_inst|hex_reader_inst|first_char~q\ & ((!\dbg_port_inst|hex_reader_inst|first_char~1_combout\) # (!\dbg_port_inst|hex_reader_inst|state.IDLE~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010001110100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	datab => \dbg_port_inst|hex_reader_inst|first_char~0_combout\,
	datac => \dbg_port_inst|hex_reader_inst|first_char~q\,
	datad => \dbg_port_inst|hex_reader_inst|first_char~1_combout\,
	combout => \dbg_port_inst|hex_reader_inst|first_char~2_combout\);

-- Location: FF_X49_Y44_N25
\dbg_port_inst|hex_reader_inst|first_char\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|first_char~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|first_char~q\);

-- Location: LCCOMB_X48_Y44_N4
\dbg_port_inst|hex_reader_inst|current_length~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length~3_combout\ = (\dbg_port_inst|hex_reader_inst|process_0~4_combout\ & (!\dbg_port_inst|hex_reader_inst|process_0~5_combout\ & \dbg_port_inst|hex_reader_inst|first_char~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|process_0~4_combout\,
	datac => \dbg_port_inst|hex_reader_inst|process_0~5_combout\,
	datad => \dbg_port_inst|hex_reader_inst|first_char~q\,
	combout => \dbg_port_inst|hex_reader_inst|current_length~3_combout\);

-- Location: LCCOMB_X47_Y48_N20
\dbg_port_inst|hex_reader_inst|current_length[5]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[5]~2_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3)) # ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & 
-- !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|current_length[5]~2_combout\);

-- Location: LCCOMB_X49_Y44_N22
\dbg_port_inst|hex_reader_inst|current_length[5]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~2_combout\) # ((!\dbg_port_inst|hex_reader_inst|state~22_combout\ & !\dbg_port_inst|hex_reader_inst|current_length~3_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000111110001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state~22_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length~3_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length[5]~2_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\);

-- Location: LCCOMB_X48_Y44_N30
\dbg_port_inst|hex_reader_inst|process_0~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~11_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & \dbg_port_inst|hex_reader_inst|first_char~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datad => \dbg_port_inst|hex_reader_inst|first_char~q\,
	combout => \dbg_port_inst|hex_reader_inst|process_0~11_combout\);

-- Location: LCCOMB_X48_Y44_N14
\dbg_port_inst|hex_reader_inst|current_length[0]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[0]~5_combout\ = (\res_n~input_o\ & (((!\dbg_port_inst|hex_reader_inst|process_0~8_combout\) # (!\dbg_port_inst|hex_reader_inst|LessThan4~0_combout\)) # (!\dbg_port_inst|hex_reader_inst|process_0~11_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~11_combout\,
	datab => \dbg_port_inst|hex_reader_inst|LessThan4~0_combout\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|hex_reader_inst|process_0~8_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[0]~5_combout\);

-- Location: LCCOMB_X49_Y44_N20
\dbg_port_inst|hex_reader_inst|current_length[0]~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[0]~10_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & (\dbg_port_inst|hex_reader_inst|state.IDLE~q\ & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	combout => \dbg_port_inst|hex_reader_inst|current_length[0]~10_combout\);

-- Location: LCCOMB_X49_Y44_N30
\dbg_port_inst|hex_reader_inst|current_length[0]~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\ = (\dbg_port_inst|hex_reader_inst|first_char~0_combout\) # ((\dbg_port_inst|hex_reader_inst|current_length[0]~5_combout\ & (\dbg_port_inst|hex_reader_inst|current_length~3_combout\ & 
-- \dbg_port_inst|hex_reader_inst|current_length[0]~10_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[0]~5_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length~3_combout\,
	datac => \dbg_port_inst|hex_reader_inst|first_char~0_combout\,
	datad => \dbg_port_inst|hex_reader_inst|current_length[0]~10_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\);

-- Location: LCCOMB_X52_Y44_N22
\dbg_port_inst|hex_reader_inst|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add1~0_combout\ = \dbg_port_inst|hex_reader_inst|current_length\(1) $ (VCC)
-- \dbg_port_inst|hex_reader_inst|Add1~1\ = CARRY(\dbg_port_inst|hex_reader_inst|current_length\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(1),
	datad => VCC,
	combout => \dbg_port_inst|hex_reader_inst|Add1~0_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add1~1\);

-- Location: LCCOMB_X49_Y44_N8
\dbg_port_inst|hex_reader_inst|process_0~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~15_combout\ = (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|process_0~15_combout\);

-- Location: LCCOMB_X49_Y44_N0
\dbg_port_inst|hex_reader_inst|current_length[1]~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[1]~12_combout\ = (\dbg_port_inst|hex_reader_inst|state.IDLE~q\ & ((\dbg_port_inst|hex_reader_inst|Add1~0_combout\) # ((!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1)) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~15_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|Add1~0_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~15_combout\,
	datac => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	combout => \dbg_port_inst|hex_reader_inst|current_length[1]~12_combout\);

-- Location: LCCOMB_X49_Y44_N16
\dbg_port_inst|hex_reader_inst|current_length[0]~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[0]~17_combout\ = (\dbg_port_inst|hex_reader_inst|state.IDLE~q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2) & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	combout => \dbg_port_inst|hex_reader_inst|current_length[0]~17_combout\);

-- Location: LCCOMB_X53_Y44_N20
\dbg_port_inst|hex_reader_inst|Add0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add0~0_combout\ = \dbg_port_inst|hex_reader_inst|current_length\(0) $ (VCC)
-- \dbg_port_inst|hex_reader_inst|Add0~1\ = CARRY(\dbg_port_inst|hex_reader_inst|current_length\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(0),
	datad => VCC,
	combout => \dbg_port_inst|hex_reader_inst|Add0~0_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add0~1\);

-- Location: LCCOMB_X50_Y44_N0
\dbg_port_inst|hex_reader_inst|Add2~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add2~0_combout\ = \dbg_port_inst|hex_reader_inst|current_length\(0) $ (VCC)
-- \dbg_port_inst|hex_reader_inst|Add2~1\ = CARRY(\dbg_port_inst|hex_reader_inst|current_length\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(0),
	datad => VCC,
	combout => \dbg_port_inst|hex_reader_inst|Add2~0_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add2~1\);

-- Location: LCCOMB_X49_Y44_N4
\dbg_port_inst|hex_reader_inst|current_length[0]~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[0]~15_combout\ = (\dbg_port_inst|hex_reader_inst|process_0~15_combout\ & (((\dbg_port_inst|hex_reader_inst|Add2~0_combout\ & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1))))) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~15_combout\ & (\dbg_port_inst|hex_reader_inst|Add0~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001011100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|Add0~0_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~15_combout\,
	datac => \dbg_port_inst|hex_reader_inst|Add2~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	combout => \dbg_port_inst|hex_reader_inst|current_length[0]~15_combout\);

-- Location: LCCOMB_X49_Y44_N6
\dbg_port_inst|hex_reader_inst|current_length[0]~16\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[0]~16_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\ & (\dbg_port_inst|hex_reader_inst|current_length[0]~15_combout\ & \dbg_port_inst|hex_reader_inst|state.IDLE~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length[0]~15_combout\,
	datac => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[0]~16_combout\);

-- Location: LCCOMB_X49_Y44_N28
\dbg_port_inst|hex_reader_inst|current_length[0]~18\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[0]~18_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[0]~16_combout\) # ((\dbg_port_inst|hex_reader_inst|current_length\(0) & ((\dbg_port_inst|hex_reader_inst|current_length[0]~17_combout\) # 
-- (!\dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length[0]~17_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length\(0),
	datad => \dbg_port_inst|hex_reader_inst|current_length[0]~16_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[0]~18_combout\);

-- Location: FF_X49_Y44_N29
\dbg_port_inst|hex_reader_inst|current_length[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|current_length[0]~18_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|current_length\(0));

-- Location: LCCOMB_X50_Y44_N2
\dbg_port_inst|hex_reader_inst|Add2~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add2~2_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(1) & (!\dbg_port_inst|hex_reader_inst|Add2~1\)) # (!\dbg_port_inst|hex_reader_inst|current_length\(1) & ((\dbg_port_inst|hex_reader_inst|Add2~1\) # (GND)))
-- \dbg_port_inst|hex_reader_inst|Add2~3\ = CARRY((!\dbg_port_inst|hex_reader_inst|Add2~1\) # (!\dbg_port_inst|hex_reader_inst|current_length\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(1),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add2~1\,
	combout => \dbg_port_inst|hex_reader_inst|Add2~2_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add2~3\);

-- Location: LCCOMB_X53_Y44_N22
\dbg_port_inst|hex_reader_inst|Add0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add0~2_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(1) & (\dbg_port_inst|hex_reader_inst|Add0~1\ & VCC)) # (!\dbg_port_inst|hex_reader_inst|current_length\(1) & (!\dbg_port_inst|hex_reader_inst|Add0~1\))
-- \dbg_port_inst|hex_reader_inst|Add0~3\ = CARRY((!\dbg_port_inst|hex_reader_inst|current_length\(1) & !\dbg_port_inst|hex_reader_inst|Add0~1\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100000101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(1),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add0~1\,
	combout => \dbg_port_inst|hex_reader_inst|Add0~2_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add0~3\);

-- Location: LCCOMB_X49_Y44_N18
\dbg_port_inst|hex_reader_inst|current_length[1]~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[1]~13_combout\ = (\dbg_port_inst|hex_reader_inst|process_0~15_combout\ & ((\dbg_port_inst|hex_reader_inst|Add2~2_combout\) # ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1))))) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~15_combout\ & (((\dbg_port_inst|hex_reader_inst|Add0~2_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110010111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|Add2~2_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~15_combout\,
	datac => \dbg_port_inst|hex_reader_inst|Add0~2_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	combout => \dbg_port_inst|hex_reader_inst|current_length[1]~13_combout\);

-- Location: LCCOMB_X49_Y44_N26
\dbg_port_inst|hex_reader_inst|current_length[1]~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[1]~14_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\ & (\dbg_port_inst|hex_reader_inst|current_length[1]~12_combout\ & 
-- ((\dbg_port_inst|hex_reader_inst|current_length[1]~13_combout\)))) # (!\dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\ & (((\dbg_port_inst|hex_reader_inst|current_length\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[0]~11_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length[1]~12_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length\(1),
	datad => \dbg_port_inst|hex_reader_inst|current_length[1]~13_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[1]~14_combout\);

-- Location: FF_X49_Y44_N27
\dbg_port_inst|hex_reader_inst|current_length[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|current_length[1]~14_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|current_length\(1));

-- Location: LCCOMB_X50_Y44_N4
\dbg_port_inst|hex_reader_inst|Add2~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add2~4_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(2) & (\dbg_port_inst|hex_reader_inst|Add2~3\ $ (GND))) # (!\dbg_port_inst|hex_reader_inst|current_length\(2) & (!\dbg_port_inst|hex_reader_inst|Add2~3\ & 
-- VCC))
-- \dbg_port_inst|hex_reader_inst|Add2~5\ = CARRY((\dbg_port_inst|hex_reader_inst|current_length\(2) & !\dbg_port_inst|hex_reader_inst|Add2~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add2~3\,
	combout => \dbg_port_inst|hex_reader_inst|Add2~4_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add2~5\);

-- Location: LCCOMB_X48_Y44_N6
\dbg_port_inst|hex_reader_inst|current_length[5]~19\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3)) # ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2)) # 
-- ((!\dbg_port_inst|hex_reader_inst|state~22_combout\ & !\dbg_port_inst|hex_reader_inst|current_length~3_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state~22_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length~3_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\);

-- Location: LCCOMB_X52_Y44_N24
\dbg_port_inst|hex_reader_inst|Add1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add1~2_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(2) & (!\dbg_port_inst|hex_reader_inst|Add1~1\)) # (!\dbg_port_inst|hex_reader_inst|current_length\(2) & ((\dbg_port_inst|hex_reader_inst|Add1~1\) # (GND)))
-- \dbg_port_inst|hex_reader_inst|Add1~3\ = CARRY((!\dbg_port_inst|hex_reader_inst|Add1~1\) # (!\dbg_port_inst|hex_reader_inst|current_length\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add1~1\,
	combout => \dbg_port_inst|hex_reader_inst|Add1~2_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add1~3\);

-- Location: LCCOMB_X52_Y44_N10
\dbg_port_inst|hex_reader_inst|Selector14~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector14~0_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (((\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\) # (\dbg_port_inst|hex_reader_inst|Add1~2_combout\)))) # 
-- (!\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (\dbg_port_inst|hex_reader_inst|Add2~4_combout\ & (!\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111010100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Add2~4_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\,
	datad => \dbg_port_inst|hex_reader_inst|Add1~2_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector14~0_combout\);

-- Location: LCCOMB_X53_Y44_N24
\dbg_port_inst|hex_reader_inst|Add0~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add0~4_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(2) & (\dbg_port_inst|hex_reader_inst|Add0~3\ $ (GND))) # (!\dbg_port_inst|hex_reader_inst|current_length\(2) & (!\dbg_port_inst|hex_reader_inst|Add0~3\ & 
-- VCC))
-- \dbg_port_inst|hex_reader_inst|Add0~5\ = CARRY((\dbg_port_inst|hex_reader_inst|current_length\(2) & !\dbg_port_inst|hex_reader_inst|Add0~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add0~3\,
	combout => \dbg_port_inst|hex_reader_inst|Add0~4_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add0~5\);

-- Location: LCCOMB_X52_Y44_N6
\dbg_port_inst|hex_reader_inst|Selector14~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector14~1_combout\ = (\dbg_port_inst|hex_reader_inst|Selector14~0_combout\ & (((!\dbg_port_inst|hex_reader_inst|current_length\(2))) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\))) # 
-- (!\dbg_port_inst|hex_reader_inst|Selector14~0_combout\ & (\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ & ((\dbg_port_inst|hex_reader_inst|Add0~4_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110111000101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|Selector14~0_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datad => \dbg_port_inst|hex_reader_inst|Add0~4_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector14~1_combout\);

-- Location: LCCOMB_X50_Y44_N12
\dbg_port_inst|hex_reader_inst|Add4~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add4~1_combout\ = \dbg_port_inst|hex_reader_inst|current_length\(2) $ (\dbg_port_inst|hex_reader_inst|current_length\(3))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datac => \dbg_port_inst|hex_reader_inst|current_length\(3),
	combout => \dbg_port_inst|hex_reader_inst|Add4~1_combout\);

-- Location: LCCOMB_X52_Y44_N26
\dbg_port_inst|hex_reader_inst|Add1~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add1~4_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(3) & (\dbg_port_inst|hex_reader_inst|Add1~3\ $ (GND))) # (!\dbg_port_inst|hex_reader_inst|current_length\(3) & (!\dbg_port_inst|hex_reader_inst|Add1~3\ & 
-- VCC))
-- \dbg_port_inst|hex_reader_inst|Add1~5\ = CARRY((\dbg_port_inst|hex_reader_inst|current_length\(3) & !\dbg_port_inst|hex_reader_inst|Add1~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(3),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add1~3\,
	combout => \dbg_port_inst|hex_reader_inst|Add1~4_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add1~5\);

-- Location: LCCOMB_X50_Y44_N6
\dbg_port_inst|hex_reader_inst|Add2~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add2~6_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(3) & (!\dbg_port_inst|hex_reader_inst|Add2~5\)) # (!\dbg_port_inst|hex_reader_inst|current_length\(3) & ((\dbg_port_inst|hex_reader_inst|Add2~5\) # (GND)))
-- \dbg_port_inst|hex_reader_inst|Add2~7\ = CARRY((!\dbg_port_inst|hex_reader_inst|Add2~5\) # (!\dbg_port_inst|hex_reader_inst|current_length\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(3),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add2~5\,
	combout => \dbg_port_inst|hex_reader_inst|Add2~6_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add2~7\);

-- Location: LCCOMB_X53_Y44_N26
\dbg_port_inst|hex_reader_inst|Add0~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add0~6_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(3) & (!\dbg_port_inst|hex_reader_inst|Add0~5\)) # (!\dbg_port_inst|hex_reader_inst|current_length\(3) & ((\dbg_port_inst|hex_reader_inst|Add0~5\) # (GND)))
-- \dbg_port_inst|hex_reader_inst|Add0~7\ = CARRY((!\dbg_port_inst|hex_reader_inst|Add0~5\) # (!\dbg_port_inst|hex_reader_inst|current_length\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(3),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add0~5\,
	combout => \dbg_port_inst|hex_reader_inst|Add0~6_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add0~7\);

-- Location: LCCOMB_X52_Y44_N16
\dbg_port_inst|hex_reader_inst|Selector13~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector13~0_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (((\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\)))) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & 
-- ((\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ & ((\dbg_port_inst|hex_reader_inst|Add0~6_combout\))) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ & (\dbg_port_inst|hex_reader_inst|Add2~6_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010010100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Add2~6_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\,
	datad => \dbg_port_inst|hex_reader_inst|Add0~6_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector13~0_combout\);

-- Location: LCCOMB_X52_Y44_N20
\dbg_port_inst|hex_reader_inst|Selector13~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector13~1_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & ((\dbg_port_inst|hex_reader_inst|Selector13~0_combout\ & (\dbg_port_inst|hex_reader_inst|Add4~1_combout\)) # 
-- (!\dbg_port_inst|hex_reader_inst|Selector13~0_combout\ & ((\dbg_port_inst|hex_reader_inst|Add1~4_combout\))))) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (((\dbg_port_inst|hex_reader_inst|Selector13~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Add4~1_combout\,
	datac => \dbg_port_inst|hex_reader_inst|Add1~4_combout\,
	datad => \dbg_port_inst|hex_reader_inst|Selector13~0_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector13~1_combout\);

-- Location: FF_X52_Y44_N21
\dbg_port_inst|hex_reader_inst|current_length[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector13~1_combout\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|current_length[2]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|current_length\(3));

-- Location: LCCOMB_X52_Y44_N14
\dbg_port_inst|hex_reader_inst|Add4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add4~0_combout\ = \dbg_port_inst|hex_reader_inst|current_length\(5) $ (((\dbg_port_inst|hex_reader_inst|current_length\(2) & (\dbg_port_inst|hex_reader_inst|current_length\(3) & 
-- \dbg_port_inst|hex_reader_inst|current_length\(4)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111110000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datab => \dbg_port_inst|hex_reader_inst|current_length\(3),
	datac => \dbg_port_inst|hex_reader_inst|current_length\(4),
	datad => \dbg_port_inst|hex_reader_inst|current_length\(5),
	combout => \dbg_port_inst|hex_reader_inst|Add4~0_combout\);

-- Location: LCCOMB_X52_Y44_N28
\dbg_port_inst|hex_reader_inst|Add1~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add1~6_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(4) & (!\dbg_port_inst|hex_reader_inst|Add1~5\)) # (!\dbg_port_inst|hex_reader_inst|current_length\(4) & ((\dbg_port_inst|hex_reader_inst|Add1~5\) # (GND)))
-- \dbg_port_inst|hex_reader_inst|Add1~7\ = CARRY((!\dbg_port_inst|hex_reader_inst|Add1~5\) # (!\dbg_port_inst|hex_reader_inst|current_length\(4)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(4),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add1~5\,
	combout => \dbg_port_inst|hex_reader_inst|Add1~6_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add1~7\);

-- Location: LCCOMB_X52_Y44_N30
\dbg_port_inst|hex_reader_inst|Add1~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add1~8_combout\ = \dbg_port_inst|hex_reader_inst|Add1~7\ $ (!\dbg_port_inst|hex_reader_inst|current_length\(5))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|current_length\(5),
	cin => \dbg_port_inst|hex_reader_inst|Add1~7\,
	combout => \dbg_port_inst|hex_reader_inst|Add1~8_combout\);

-- Location: LCCOMB_X53_Y44_N28
\dbg_port_inst|hex_reader_inst|Add0~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add0~8_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(4) & (\dbg_port_inst|hex_reader_inst|Add0~7\ $ (GND))) # (!\dbg_port_inst|hex_reader_inst|current_length\(4) & (!\dbg_port_inst|hex_reader_inst|Add0~7\ & 
-- VCC))
-- \dbg_port_inst|hex_reader_inst|Add0~9\ = CARRY((\dbg_port_inst|hex_reader_inst|current_length\(4) & !\dbg_port_inst|hex_reader_inst|Add0~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(4),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add0~7\,
	combout => \dbg_port_inst|hex_reader_inst|Add0~8_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add0~9\);

-- Location: LCCOMB_X53_Y44_N30
\dbg_port_inst|hex_reader_inst|Add0~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add0~10_combout\ = \dbg_port_inst|hex_reader_inst|Add0~9\ $ (\dbg_port_inst|hex_reader_inst|current_length\(5))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|current_length\(5),
	cin => \dbg_port_inst|hex_reader_inst|Add0~9\,
	combout => \dbg_port_inst|hex_reader_inst|Add0~10_combout\);

-- Location: LCCOMB_X50_Y44_N8
\dbg_port_inst|hex_reader_inst|Add2~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add2~8_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(4) & (\dbg_port_inst|hex_reader_inst|Add2~7\ $ (GND))) # (!\dbg_port_inst|hex_reader_inst|current_length\(4) & (!\dbg_port_inst|hex_reader_inst|Add2~7\ & 
-- VCC))
-- \dbg_port_inst|hex_reader_inst|Add2~9\ = CARRY((\dbg_port_inst|hex_reader_inst|current_length\(4) & !\dbg_port_inst|hex_reader_inst|Add2~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(4),
	datad => VCC,
	cin => \dbg_port_inst|hex_reader_inst|Add2~7\,
	combout => \dbg_port_inst|hex_reader_inst|Add2~8_combout\,
	cout => \dbg_port_inst|hex_reader_inst|Add2~9\);

-- Location: LCCOMB_X50_Y44_N10
\dbg_port_inst|hex_reader_inst|Add2~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Add2~10_combout\ = \dbg_port_inst|hex_reader_inst|Add2~9\ $ (\dbg_port_inst|hex_reader_inst|current_length\(5))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|current_length\(5),
	cin => \dbg_port_inst|hex_reader_inst|Add2~9\,
	combout => \dbg_port_inst|hex_reader_inst|Add2~10_combout\);

-- Location: LCCOMB_X52_Y44_N12
\dbg_port_inst|hex_reader_inst|Selector11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector11~0_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\)) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & 
-- ((\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ & (\dbg_port_inst|hex_reader_inst|Add0~10_combout\)) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ & ((\dbg_port_inst|hex_reader_inst|Add2~10_combout\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100111001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\,
	datac => \dbg_port_inst|hex_reader_inst|Add0~10_combout\,
	datad => \dbg_port_inst|hex_reader_inst|Add2~10_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector11~0_combout\);

-- Location: LCCOMB_X52_Y44_N18
\dbg_port_inst|hex_reader_inst|Selector11~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector11~1_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & ((\dbg_port_inst|hex_reader_inst|Selector11~0_combout\ & (\dbg_port_inst|hex_reader_inst|Add4~0_combout\)) # 
-- (!\dbg_port_inst|hex_reader_inst|Selector11~0_combout\ & ((\dbg_port_inst|hex_reader_inst|Add1~8_combout\))))) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (((\dbg_port_inst|hex_reader_inst|Selector11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Add4~0_combout\,
	datac => \dbg_port_inst|hex_reader_inst|Add1~8_combout\,
	datad => \dbg_port_inst|hex_reader_inst|Selector11~0_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector11~1_combout\);

-- Location: FF_X52_Y44_N19
\dbg_port_inst|hex_reader_inst|current_length[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector11~1_combout\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|current_length[2]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|current_length\(5));

-- Location: LCCOMB_X53_Y44_N16
\dbg_port_inst|hex_reader_inst|current_length[2]~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[2]~6_combout\ = ((!\dbg_port_inst|hex_reader_inst|current_length\(1) & (!\dbg_port_inst|hex_reader_inst|current_length\(3) & !\dbg_port_inst|hex_reader_inst|current_length\(2)))) # 
-- (!\dbg_port_inst|hex_reader_inst|current_length\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(1),
	datab => \dbg_port_inst|hex_reader_inst|current_length\(3),
	datac => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datad => \dbg_port_inst|hex_reader_inst|current_length\(4),
	combout => \dbg_port_inst|hex_reader_inst|current_length[2]~6_combout\);

-- Location: LCCOMB_X53_Y44_N10
\dbg_port_inst|hex_reader_inst|current_length[2]~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[2]~7_combout\ = (!\dbg_port_inst|hex_reader_inst|current_length\(5) & \dbg_port_inst|hex_reader_inst|current_length[2]~6_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|current_length\(5),
	datad => \dbg_port_inst|hex_reader_inst|current_length[2]~6_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[2]~7_combout\);

-- Location: LCCOMB_X48_Y44_N8
\dbg_port_inst|hex_reader_inst|current_length[2]~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[2]~8_combout\ = (\dbg_port_inst|hex_reader_inst|state~22_combout\ & (!\dbg_port_inst|hex_reader_inst|process_0~17_combout\)) # (!\dbg_port_inst|hex_reader_inst|state~22_combout\ & 
-- ((\dbg_port_inst|hex_reader_inst|current_length[2]~7_combout\) # ((!\dbg_port_inst|hex_reader_inst|process_0~17_combout\ & \dbg_port_inst|hex_reader_inst|first_char~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101111101010100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~17_combout\,
	datab => \dbg_port_inst|hex_reader_inst|first_char~q\,
	datac => \dbg_port_inst|hex_reader_inst|state~22_combout\,
	datad => \dbg_port_inst|hex_reader_inst|current_length[2]~7_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[2]~8_combout\);

-- Location: LCCOMB_X49_Y44_N2
\dbg_port_inst|hex_reader_inst|current_length[2]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|current_length[2]~9_combout\ = (\dbg_port_inst|hex_reader_inst|first_char~0_combout\) # ((\dbg_port_inst|hex_reader_inst|current_length[2]~8_combout\ & (\dbg_port_inst|hex_reader_inst|Selector7~2_combout\ & 
-- \dbg_port_inst|hex_reader_inst|current_length[0]~5_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[2]~8_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Selector7~2_combout\,
	datac => \dbg_port_inst|hex_reader_inst|first_char~0_combout\,
	datad => \dbg_port_inst|hex_reader_inst|current_length[0]~5_combout\,
	combout => \dbg_port_inst|hex_reader_inst|current_length[2]~9_combout\);

-- Location: FF_X52_Y44_N7
\dbg_port_inst|hex_reader_inst|current_length[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector14~1_combout\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|current_length[2]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|current_length\(2));

-- Location: LCCOMB_X52_Y44_N0
\dbg_port_inst|hex_reader_inst|Selector12~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector12~0_combout\ = \dbg_port_inst|hex_reader_inst|current_length\(4) $ (((\dbg_port_inst|hex_reader_inst|current_length\(2) & \dbg_port_inst|hex_reader_inst|current_length\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100001111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datab => \dbg_port_inst|hex_reader_inst|current_length\(3),
	datac => \dbg_port_inst|hex_reader_inst|current_length\(4),
	combout => \dbg_port_inst|hex_reader_inst|Selector12~0_combout\);

-- Location: LCCOMB_X52_Y44_N2
\dbg_port_inst|hex_reader_inst|Selector12~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector12~1_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & ((\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ & (\dbg_port_inst|hex_reader_inst|Selector12~0_combout\)) # 
-- (!\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\ & ((\dbg_port_inst|hex_reader_inst|Add1~6_combout\))))) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (((\dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101101011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Selector12~0_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length[5]~19_combout\,
	datad => \dbg_port_inst|hex_reader_inst|Add1~6_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector12~1_combout\);

-- Location: LCCOMB_X52_Y44_N8
\dbg_port_inst|hex_reader_inst|Selector12~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector12~2_combout\ = (\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & (\dbg_port_inst|hex_reader_inst|Selector12~1_combout\)) # (!\dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\ & 
-- ((\dbg_port_inst|hex_reader_inst|Selector12~1_combout\ & ((\dbg_port_inst|hex_reader_inst|Add0~8_combout\))) # (!\dbg_port_inst|hex_reader_inst|Selector12~1_combout\ & (\dbg_port_inst|hex_reader_inst|Add2~8_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length[5]~4_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Selector12~1_combout\,
	datac => \dbg_port_inst|hex_reader_inst|Add2~8_combout\,
	datad => \dbg_port_inst|hex_reader_inst|Add0~8_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector12~2_combout\);

-- Location: FF_X52_Y44_N9
\dbg_port_inst|hex_reader_inst|current_length[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector12~2_combout\,
	sclr => \dbg_port_inst|hex_reader_inst|ALT_INV_state.PROCESS_CHAR~q\,
	ena => \dbg_port_inst|hex_reader_inst|current_length[2]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|current_length\(4));

-- Location: LCCOMB_X50_Y44_N28
\dbg_port_inst|hex_reader_inst|process_0~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~12_combout\ = (!\dbg_port_inst|hex_reader_inst|current_length\(2) & (!\dbg_port_inst|hex_reader_inst|current_length\(3) & ((!\dbg_port_inst|hex_reader_inst|current_length\(0)) # 
-- (!\dbg_port_inst|hex_reader_inst|current_length\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(1),
	datab => \dbg_port_inst|hex_reader_inst|current_length\(0),
	datac => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datad => \dbg_port_inst|hex_reader_inst|current_length\(3),
	combout => \dbg_port_inst|hex_reader_inst|process_0~12_combout\);

-- Location: LCCOMB_X42_Y49_N4
\dbg_port_inst|hex_writer_width~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width~3_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & \dbg_port_inst|hex_reader_inst|value\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_writer_width~3_combout\);

-- Location: LCCOMB_X47_Y48_N22
\dbg_port_inst|hex_reader_max_length[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_max_length[0]~0_combout\ = (\dbg_port_inst|Selector3~1_combout\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datab => \dbg_port_inst|Selector3~1_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_max_length[0]~0_combout\);

-- Location: LCCOMB_X42_Y48_N20
\dbg_port_inst|hex_reader_max_length[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_max_length[0]~1_combout\ = (\dbg_port_inst|hex_reader_inst|value\(1) & ((\dbg_port_inst|hex_reader_inst|value\(0) & (!\dbg_port_inst|hex_reader_inst|value\(3))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & 
-- ((!\dbg_port_inst|hex_reader_inst|value\(2)))))) # (!\dbg_port_inst|hex_reader_inst|value\(1) & (\dbg_port_inst|hex_reader_inst|value\(3) & ((!\dbg_port_inst|hex_reader_inst|value\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000000111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|hex_reader_max_length[0]~1_combout\);

-- Location: LCCOMB_X42_Y48_N30
\dbg_port_inst|hex_reader_max_length[0]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_max_length[0]~2_combout\ = (\res_n~input_o\ & ((\dbg_port_inst|hex_reader_max_length[0]~0_combout\) # ((\dbg_port_inst|write_address[3]~0_combout\ & \dbg_port_inst|hex_reader_max_length[0]~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010100010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \res_n~input_o\,
	datab => \dbg_port_inst|write_address[3]~0_combout\,
	datac => \dbg_port_inst|hex_reader_max_length[0]~0_combout\,
	datad => \dbg_port_inst|hex_reader_max_length[0]~1_combout\,
	combout => \dbg_port_inst|hex_reader_max_length[0]~2_combout\);

-- Location: FF_X42_Y49_N5
\dbg_port_inst|hex_reader_max_length[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_width~3_combout\,
	sclr => \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	ena => \dbg_port_inst|hex_reader_max_length[0]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_max_length\(0));

-- Location: LCCOMB_X42_Y48_N0
\dbg_port_inst|hex_reader_max_length[0]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_max_length[0]~3_combout\ = (\dbg_port_inst|hex_reader_inst|value\(1) & !\dbg_port_inst|hex_reader_inst|value\(3))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(3),
	combout => \dbg_port_inst|hex_reader_max_length[0]~3_combout\);

-- Location: FF_X42_Y48_N1
\dbg_port_inst|hex_reader_max_length[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_max_length[0]~3_combout\,
	asdata => \~GND~combout\,
	sclr => \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	sload => \dbg_port_inst|hex_reader_inst|value\(0),
	ena => \dbg_port_inst|hex_reader_max_length[0]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_max_length\(1));

-- Location: LCCOMB_X50_Y44_N20
\dbg_port_inst|hex_reader_inst|LessThan11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|LessThan11~0_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(1) & (((!\dbg_port_inst|hex_reader_max_length\(0) & \dbg_port_inst|hex_reader_inst|current_length\(0))) # (!\dbg_port_inst|hex_reader_max_length\(1)))) 
-- # (!\dbg_port_inst|hex_reader_inst|current_length\(1) & (!\dbg_port_inst|hex_reader_max_length\(0) & (!\dbg_port_inst|hex_reader_max_length\(1) & \dbg_port_inst|hex_reader_inst|current_length\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010101100001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(1),
	datab => \dbg_port_inst|hex_reader_max_length\(0),
	datac => \dbg_port_inst|hex_reader_max_length\(1),
	datad => \dbg_port_inst|hex_reader_inst|current_length\(0),
	combout => \dbg_port_inst|hex_reader_inst|LessThan11~0_combout\);

-- Location: LCCOMB_X45_Y46_N16
\dbg_port_inst|Selector15~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector15~0_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(2) & \dbg_port_inst|hex_reader_inst|value\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|Selector15~0_combout\);

-- Location: FF_X45_Y46_N17
\dbg_port_inst|hex_reader_max_length[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector15~0_combout\,
	asdata => VCC,
	sload => \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	ena => \dbg_port_inst|hex_reader_max_length[0]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_max_length\(2));

-- Location: LCCOMB_X50_Y44_N30
\dbg_port_inst|hex_reader_inst|LessThan11~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|LessThan11~1_combout\ = (\dbg_port_inst|hex_reader_inst|LessThan11~0_combout\ & ((\dbg_port_inst|hex_reader_inst|current_length\(2)) # (!\dbg_port_inst|hex_reader_max_length\(2)))) # 
-- (!\dbg_port_inst|hex_reader_inst|LessThan11~0_combout\ & (\dbg_port_inst|hex_reader_inst|current_length\(2) & !\dbg_port_inst|hex_reader_max_length\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|LessThan11~0_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length\(2),
	datad => \dbg_port_inst|hex_reader_max_length\(2),
	combout => \dbg_port_inst|hex_reader_inst|LessThan11~1_combout\);

-- Location: LCCOMB_X42_Y49_N26
\dbg_port_inst|hex_writer_width[0]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_width[0]~2_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(0) & !\dbg_port_inst|hex_reader_inst|value\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_width[0]~2_combout\);

-- Location: FF_X42_Y49_N27
\dbg_port_inst|hex_reader_max_length[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_width[0]~2_combout\,
	sclr => \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	ena => \dbg_port_inst|hex_reader_max_length[0]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_max_length\(3));

-- Location: LCCOMB_X50_Y44_N24
\dbg_port_inst|hex_reader_inst|LessThan11~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|LessThan11~2_combout\ = (\dbg_port_inst|hex_reader_inst|LessThan11~1_combout\ & ((\dbg_port_inst|hex_reader_inst|current_length\(3)) # (!\dbg_port_inst|hex_reader_max_length\(3)))) # 
-- (!\dbg_port_inst|hex_reader_inst|LessThan11~1_combout\ & (\dbg_port_inst|hex_reader_inst|current_length\(3) & !\dbg_port_inst|hex_reader_max_length\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|LessThan11~1_combout\,
	datac => \dbg_port_inst|hex_reader_inst|current_length\(3),
	datad => \dbg_port_inst|hex_reader_max_length\(3),
	combout => \dbg_port_inst|hex_reader_inst|LessThan11~2_combout\);

-- Location: LCCOMB_X42_Y49_N14
\dbg_port_inst|Selector13~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector13~0_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(0) & \dbg_port_inst|hex_reader_inst|value\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|Selector13~0_combout\);

-- Location: LCCOMB_X42_Y49_N16
\dbg_port_inst|hex_reader_max_length[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_max_length[4]~feeder_combout\ = \dbg_port_inst|Selector13~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|Selector13~0_combout\,
	combout => \dbg_port_inst|hex_reader_max_length[4]~feeder_combout\);

-- Location: FF_X42_Y49_N17
\dbg_port_inst|hex_reader_max_length[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_max_length[4]~feeder_combout\,
	sclr => \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	ena => \dbg_port_inst|hex_reader_max_length[0]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_max_length\(4));

-- Location: LCCOMB_X50_Y44_N26
\dbg_port_inst|hex_reader_inst|LessThan11~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|LessThan11~3_combout\ = (\dbg_port_inst|hex_reader_inst|current_length\(5)) # ((\dbg_port_inst|hex_reader_inst|LessThan11~2_combout\ & ((\dbg_port_inst|hex_reader_inst|current_length\(4)) # 
-- (!\dbg_port_inst|hex_reader_max_length\(4)))) # (!\dbg_port_inst|hex_reader_inst|LessThan11~2_combout\ & (!\dbg_port_inst|hex_reader_max_length\(4) & \dbg_port_inst|hex_reader_inst|current_length\(4))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111110101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(5),
	datab => \dbg_port_inst|hex_reader_inst|LessThan11~2_combout\,
	datac => \dbg_port_inst|hex_reader_max_length\(4),
	datad => \dbg_port_inst|hex_reader_inst|current_length\(4),
	combout => \dbg_port_inst|hex_reader_inst|LessThan11~3_combout\);

-- Location: LCCOMB_X50_Y44_N22
\dbg_port_inst|hex_reader_inst|process_0~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~13_combout\ = (!\dbg_port_inst|hex_reader_max_length\(1) & (!\dbg_port_inst|hex_reader_max_length\(0) & (!\dbg_port_inst|hex_reader_max_length\(2) & !\dbg_port_inst|hex_reader_inst|current_length\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_max_length\(1),
	datab => \dbg_port_inst|hex_reader_max_length\(0),
	datac => \dbg_port_inst|hex_reader_max_length\(2),
	datad => \dbg_port_inst|hex_reader_inst|current_length\(5),
	combout => \dbg_port_inst|hex_reader_inst|process_0~13_combout\);

-- Location: LCCOMB_X50_Y44_N16
\dbg_port_inst|hex_reader_inst|process_0~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~14_combout\ = (\dbg_port_inst|hex_reader_inst|process_0~13_combout\ & (!\dbg_port_inst|hex_reader_max_length\(4) & !\dbg_port_inst|hex_reader_max_length\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~13_combout\,
	datab => \dbg_port_inst|hex_reader_max_length\(4),
	datac => \dbg_port_inst|hex_reader_max_length\(3),
	combout => \dbg_port_inst|hex_reader_inst|process_0~14_combout\);

-- Location: LCCOMB_X50_Y44_N18
\dbg_port_inst|hex_reader_inst|Selector7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector7~0_combout\ = (\dbg_port_inst|hex_reader_inst|LessThan11~3_combout\ & (((\dbg_port_inst|hex_reader_inst|current_length\(4) & !\dbg_port_inst|hex_reader_inst|process_0~12_combout\)) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~14_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|current_length\(4),
	datab => \dbg_port_inst|hex_reader_inst|process_0~12_combout\,
	datac => \dbg_port_inst|hex_reader_inst|LessThan11~3_combout\,
	datad => \dbg_port_inst|hex_reader_inst|process_0~14_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector7~0_combout\);

-- Location: LCCOMB_X47_Y44_N14
\dbg_port_inst|hex_reader_inst|Selector7~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector7~3_combout\ = (\dbg_port_inst|hex_reader_inst|Selector7~2_combout\ & ((\dbg_port_inst|hex_reader_inst|state~22_combout\) # ((\dbg_port_inst|hex_reader_inst|Selector7~0_combout\ & 
-- \dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH~q\)))) # (!\dbg_port_inst|hex_reader_inst|Selector7~2_combout\ & (\dbg_port_inst|hex_reader_inst|Selector7~0_combout\ & ((\dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110110010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|Selector7~2_combout\,
	datab => \dbg_port_inst|hex_reader_inst|Selector7~0_combout\,
	datac => \dbg_port_inst|hex_reader_inst|state~22_combout\,
	datad => \dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector7~3_combout\);

-- Location: FF_X47_Y44_N15
\dbg_port_inst|hex_reader_inst|state.COMPLETE_ERROR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector7~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|state.COMPLETE_ERROR~q\);

-- Location: FF_X45_Y48_N29
\dbg_port_inst|hex_reader_inst|parse_error\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|state.COMPLETE_ERROR~q\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|parse_error~q\);

-- Location: LCCOMB_X45_Y48_N12
\dbg_port_inst|fsm_state~31\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|fsm_state~31_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\) # (\dbg_port_inst|hex_reader_inst|parse_error~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|done~q\,
	datad => \dbg_port_inst|hex_reader_inst|parse_error~q\,
	combout => \dbg_port_inst|fsm_state~31_combout\);

-- Location: LCCOMB_X45_Y48_N4
\dbg_port_inst|Selector0~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~4_combout\ = (\dbg_port_inst|hex_reader_inst|abort~q\ & ((\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\) # ((\dbg_port_inst|fsm_state.READ_OPERATION~q\) # (\dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\,
	datab => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datac => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_ADDRESS~q\,
	datad => \dbg_port_inst|hex_reader_inst|abort~q\,
	combout => \dbg_port_inst|Selector0~4_combout\);

-- Location: LCCOMB_X39_Y48_N12
\dbg_port_inst|Selector21~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector21~0_combout\ = (\dbg_port_inst|fsm_state.PRINT_ERROR~q\) # ((!\dbg_port_inst|fsm_state.PRINT_OK~q\ & \dbg_port_inst|str_writer_str[1][4]~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.PRINT_OK~q\,
	datac => \dbg_port_inst|str_writer_str[1][4]~q\,
	datad => \dbg_port_inst|fsm_state.PRINT_ERROR~q\,
	combout => \dbg_port_inst|Selector21~0_combout\);

-- Location: FF_X39_Y48_N13
\dbg_port_inst|str_writer_str[1][4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector21~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_str[1][4]~q\);

-- Location: LCCOMB_X39_Y48_N22
\dbg_port_inst|str_writer_inst|Selector5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Selector5~0_combout\ = (!\dbg_port_inst|str_writer_inst|idx\(0) & \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|str_writer_inst|idx\(0),
	datad => \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\,
	combout => \dbg_port_inst|str_writer_inst|Selector5~0_combout\);

-- Location: LCCOMB_X39_Y48_N10
\dbg_port_inst|str_writer_inst|Selector0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Selector0~0_combout\ = (!\dbg_port_inst|str_writer_inst|state.COMPLETE~q\ & ((\dbg_port_inst|str_writer_inst|state.IDLE~q\) # (\dbg_port_inst|str_writer_start~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|str_writer_inst|state.COMPLETE~q\,
	datac => \dbg_port_inst|str_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|str_writer_start~q\,
	combout => \dbg_port_inst|str_writer_inst|Selector0~0_combout\);

-- Location: FF_X39_Y48_N11
\dbg_port_inst|str_writer_inst|state.IDLE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Selector0~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|state.IDLE~q\);

-- Location: LCCOMB_X39_Y48_N14
\dbg_port_inst|str_writer_inst|idx[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|idx[0]~0_combout\ = (\res_n~input_o\ & ((\dbg_port_inst|str_writer_inst|tx_wr~0_combout\) # ((!\dbg_port_inst|str_writer_inst|state.IDLE~q\ & \dbg_port_inst|str_writer_start~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|state.IDLE~q\,
	datab => \dbg_port_inst|str_writer_start~q\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	combout => \dbg_port_inst|str_writer_inst|idx[0]~0_combout\);

-- Location: FF_X39_Y48_N23
\dbg_port_inst|str_writer_inst|idx[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Selector5~0_combout\,
	ena => \dbg_port_inst|str_writer_inst|idx[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|idx\(0));

-- Location: LCCOMB_X39_Y48_N2
\dbg_port_inst|str_writer_inst|Selector4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Selector4~0_combout\ = (\dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\ & (\dbg_port_inst|str_writer_inst|idx\(1) $ (\dbg_port_inst|str_writer_inst|idx\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|str_writer_inst|idx\(1),
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Selector4~0_combout\);

-- Location: FF_X39_Y48_N3
\dbg_port_inst|str_writer_inst|idx[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Selector4~0_combout\,
	ena => \dbg_port_inst|str_writer_inst|idx[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|idx\(1));

-- Location: LCCOMB_X39_Y48_N20
\dbg_port_inst|str_writer_inst|Selector3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Selector3~0_combout\ = (\dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\ & (\dbg_port_inst|str_writer_inst|idx\(2) $ (((\dbg_port_inst|str_writer_inst|idx\(1) & \dbg_port_inst|str_writer_inst|idx\(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100100011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datab => \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|str_writer_inst|idx\(2),
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Selector3~0_combout\);

-- Location: FF_X39_Y48_N21
\dbg_port_inst|str_writer_inst|idx[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Selector3~0_combout\,
	ena => \dbg_port_inst|str_writer_inst|idx[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|idx\(2));

-- Location: LCCOMB_X39_Y48_N30
\dbg_port_inst|str_writer_inst|state~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|state~8_combout\ = (\dbg_port_inst|str_writer_str[1][4]~q\ & (((!\dbg_port_inst|str_writer_inst|idx\(1))) # (!\dbg_port_inst|str_writer_inst|idx\(2)))) # (!\dbg_port_inst|str_writer_str[1][4]~q\ & 
-- (!\dbg_port_inst|str_writer_inst|idx\(2) & ((!\dbg_port_inst|str_writer_inst|idx\(0)) # (!\dbg_port_inst|str_writer_inst|idx\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010101100111011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_str[1][4]~q\,
	datab => \dbg_port_inst|str_writer_inst|idx\(2),
	datac => \dbg_port_inst|str_writer_inst|idx\(1),
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|state~8_combout\);

-- Location: LCCOMB_X39_Y48_N28
\dbg_port_inst|str_writer_inst|Selector2~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Selector2~0_combout\ = (!\dbg_port_inst|str_writer_inst|tx_wr~q\ & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ & (!\dbg_port_inst|str_writer_inst|state~8_combout\ & 
-- \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|tx_wr~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datac => \dbg_port_inst|str_writer_inst|state~8_combout\,
	datad => \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\,
	combout => \dbg_port_inst|str_writer_inst|Selector2~0_combout\);

-- Location: FF_X39_Y48_N29
\dbg_port_inst|str_writer_inst|state.COMPLETE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Selector2~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|state.COMPLETE~q\);

-- Location: FF_X46_Y48_N17
\dbg_port_inst|str_writer_inst|done\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|str_writer_inst|state.COMPLETE~q\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|done~q\);

-- Location: LCCOMB_X46_Y48_N20
\dbg_port_inst|Selector10~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector10~0_combout\ = (\dbg_port_inst|fsm_state.PRINT_OK~q\) # ((\dbg_port_inst|fsm_state.PRINT_ERROR~q\) # ((\dbg_port_inst|fsm_state.WAIT_PRINT_STR~q\ & !\dbg_port_inst|str_writer_inst|done~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111011111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.PRINT_OK~q\,
	datab => \dbg_port_inst|fsm_state.PRINT_ERROR~q\,
	datac => \dbg_port_inst|fsm_state.WAIT_PRINT_STR~q\,
	datad => \dbg_port_inst|str_writer_inst|done~q\,
	combout => \dbg_port_inst|Selector10~0_combout\);

-- Location: FF_X46_Y48_N21
\dbg_port_inst|fsm_state.WAIT_PRINT_STR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector10~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.WAIT_PRINT_STR~q\);

-- Location: LCCOMB_X46_Y48_N16
\dbg_port_inst|Selector0~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~5_combout\ = (\dbg_port_inst|fsm_state.WAIT_PRINT_STR~q\ & (((\dbg_port_inst|str_writer_inst|done~q\)))) # (!\dbg_port_inst|fsm_state.WAIT_PRINT_STR~q\ & (!\dbg_port_inst|fsm_state~31_combout\ & 
-- (\dbg_port_inst|Selector0~4_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state~31_combout\,
	datab => \dbg_port_inst|Selector0~4_combout\,
	datac => \dbg_port_inst|str_writer_inst|done~q\,
	datad => \dbg_port_inst|fsm_state.WAIT_PRINT_STR~q\,
	combout => \dbg_port_inst|Selector0~5_combout\);

-- Location: LCCOMB_X46_Y48_N26
\dbg_port_inst|Selector0~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~8_combout\ = (\dbg_port_inst|Selector0~1_combout\ & ((\dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\ & ((\dbg_port_inst|ci_hex_writer_inst|done~q\))) # (!\dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\ & 
-- (\dbg_port_inst|Selector0~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Selector0~5_combout\,
	datab => \dbg_port_inst|fsm_state.WAIT_HEX_WRITER~q\,
	datac => \dbg_port_inst|Selector0~1_combout\,
	datad => \dbg_port_inst|ci_hex_writer_inst|done~q\,
	combout => \dbg_port_inst|Selector0~8_combout\);

-- Location: LCCOMB_X46_Y48_N28
\dbg_port_inst|Selector0~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~7_combout\ = (\dbg_port_inst|fsm_state.READ_COMMAND~q\ & (\dbg_port_inst|Mux0~1_combout\ & (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4) & \dbg_port_inst|Mux0~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.READ_COMMAND~q\,
	datab => \dbg_port_inst|Mux0~1_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datad => \dbg_port_inst|Mux0~0_combout\,
	combout => \dbg_port_inst|Selector0~7_combout\);

-- Location: LCCOMB_X46_Y48_N30
\dbg_port_inst|Selector0~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~9_combout\ = (!\dbg_port_inst|Selector0~8_combout\ & (!\dbg_port_inst|Selector0~7_combout\ & ((\dbg_port_inst|fsm_state.IDLE~q\) # (\dbg_port_inst|Selector0~6_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Selector0~8_combout\,
	datab => \dbg_port_inst|Selector0~7_combout\,
	datac => \dbg_port_inst|fsm_state.IDLE~q\,
	datad => \dbg_port_inst|Selector0~6_combout\,
	combout => \dbg_port_inst|Selector0~9_combout\);

-- Location: FF_X46_Y48_N31
\dbg_port_inst|fsm_state.IDLE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector0~9_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.IDLE~q\);

-- Location: LCCOMB_X46_Y48_N24
\dbg_port_inst|Selector0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector0~0_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\ & !\dbg_port_inst|fsm_state.IDLE~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\,
	datad => \dbg_port_inst|fsm_state.IDLE~q\,
	combout => \dbg_port_inst|Selector0~0_combout\);

-- Location: FF_X46_Y48_N25
\dbg_port_inst|fsm_rx_rd\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_rx_rd~q\);

-- Location: LCCOMB_X47_Y47_N18
\dbg_port_inst|serial_port_inst|receiver_fifo|full_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~2_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0) & (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1))))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0) & (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1) $ (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001001010000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(1),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~2_combout\);

-- Location: LCCOMB_X47_Y47_N28
\dbg_port_inst|serial_port_inst|receiver_fifo|full_next~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~3_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|full_next~2_combout\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(2) $ 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|Add1~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001100100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(2),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~3_combout\);

-- Location: LCCOMB_X47_Y43_N18
\dbg_port_inst|serial_port_inst|receiver_fifo|full_next~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~4_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|full_next~3_combout\ & (\dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\ & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(3) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|Add1~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~3_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(3),
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~1_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~4_combout\);

-- Location: LCCOMB_X47_Y43_N20
\dbg_port_inst|serial_port_inst|receiver_fifo|full_next~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~5_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|full_next~4_combout\) # ((!\dbg_port_inst|hex_reader_inst|rx_rd~q\ & (!\dbg_port_inst|fsm_rx_rd~q\ & 
-- \dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|rx_rd~q\,
	datab => \dbg_port_inst|fsm_rx_rd~q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~4_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~5_combout\);

-- Location: FF_X47_Y43_N21
\dbg_port_inst|serial_port_inst|receiver_fifo|full_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|full_next~5_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\);

-- Location: LCCOMB_X47_Y43_N14
\dbg_port_inst|serial_port_inst|receiver_fifo|wr_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\ = (\dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\ & !\dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|receiver_inst|data_new~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|full_int~q\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\);

-- Location: FF_X46_Y47_N29
\dbg_port_inst|serial_port_inst|receiver_fifo|write_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0));

-- Location: LCCOMB_X46_Y47_N30
\dbg_port_inst|serial_port_inst|receiver_fifo|Add1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~2_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1) $ (\dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~2_combout\);

-- Location: FF_X46_Y47_N31
\dbg_port_inst|serial_port_inst|receiver_fifo|write_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|Add1~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1));

-- Location: FF_X47_Y47_N13
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(1),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(3));

-- Location: LCCOMB_X47_Y47_N8
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[2]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\ = !\dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\);

-- Location: FF_X47_Y47_N9
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(2));

-- Location: FF_X47_Y47_N15
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(4));

-- Location: FF_X47_Y47_N11
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(0),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(1));

-- Location: LCCOMB_X47_Y47_N14
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~23_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(3) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(4) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(2) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(1))))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(3) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(4) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(2) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(3),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(2),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(4),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(1),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~23_combout\);

-- Location: FF_X47_Y43_N3
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_fifo|wr_int~combout\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(0));

-- Location: LCCOMB_X46_Y47_N26
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(3),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\);

-- Location: FF_X46_Y47_N27
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(7));

-- Location: LCCOMB_X47_Y47_N2
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[8]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\);

-- Location: FF_X47_Y47_N3
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(8));

-- Location: FF_X47_Y47_N21
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_fifo|Add0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(6));

-- Location: LCCOMB_X46_Y47_N16
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\ = \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|write_address\(2),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\);

-- Location: FF_X46_Y47_N17
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(5));

-- Location: LCCOMB_X47_Y47_N20
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~24_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(7) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(8) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(6) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(5))))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(7) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(8) & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(6) $ (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(5)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001000000001001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(7),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(8),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(6),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(5),
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~24_combout\);

-- Location: LCCOMB_X47_Y47_N10
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~23_combout\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(0) & 
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~24_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~23_combout\,
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(0),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~24_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\);

-- Location: FF_X47_Y47_N31
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(4),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(17));

-- Location: FF_X50_Y47_N29
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~18\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|receiver_inst|data_out\(4),
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~18_q\);

-- Location: LCCOMB_X50_Y47_N28
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~37\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~37_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~18_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~18_q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~37_combout\);

-- Location: LCCOMB_X47_Y47_N0
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~38\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~38_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(18) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(17))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~37_combout\))))) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(18) & (((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(17)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(18),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~25_combout\,
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram_rtl_0_bypass\(17),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~37_combout\,
	combout => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~38_combout\);

-- Location: FF_X47_Y47_N1
\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|ram~38_combout\,
	ena => \dbg_port_inst|serial_port_inst|receiver_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4));

-- Location: LCCOMB_X47_Y48_N16
\dbg_port_inst|hex_reader_inst|process_0~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|process_0~5_combout\ = ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3) & ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1)) # 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2))))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010111010101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|process_0~5_combout\);

-- Location: LCCOMB_X47_Y48_N2
\dbg_port_inst|hex_reader_inst|state~20\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|state~20_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3)) # ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & 
-- (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2))) # (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0) & 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1) & !\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100011110001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(0),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(2),
	combout => \dbg_port_inst|hex_reader_inst|state~20_combout\);

-- Location: LCCOMB_X48_Y44_N10
\dbg_port_inst|hex_reader_inst|state~21\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|state~21_combout\ = (\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7)) # ((\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4)) # 
-- (!\dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111111101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(7),
	datab => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(4),
	datac => \dbg_port_inst|serial_port_inst|receiver_fifo|memory_inst|rd1_data\(6),
	combout => \dbg_port_inst|hex_reader_inst|state~21_combout\);

-- Location: LCCOMB_X48_Y44_N20
\dbg_port_inst|hex_reader_inst|state~22\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|state~22_combout\ = (\dbg_port_inst|hex_reader_inst|process_0~5_combout\ & (((\dbg_port_inst|hex_reader_inst|state~20_combout\) # (\dbg_port_inst|hex_reader_inst|state~21_combout\)))) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~5_combout\ & (!\dbg_port_inst|hex_reader_inst|process_0~4_combout\ & ((\dbg_port_inst|hex_reader_inst|state~20_combout\) # (\dbg_port_inst|hex_reader_inst|state~21_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101110110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|process_0~5_combout\,
	datab => \dbg_port_inst|hex_reader_inst|process_0~4_combout\,
	datac => \dbg_port_inst|hex_reader_inst|state~20_combout\,
	datad => \dbg_port_inst|hex_reader_inst|state~21_combout\,
	combout => \dbg_port_inst|hex_reader_inst|state~22_combout\);

-- Location: LCCOMB_X47_Y44_N4
\dbg_port_inst|hex_reader_inst|expect_leading_space~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|expect_leading_space~3_combout\ = (\dbg_port_inst|hex_reader_inst|state.IDLE~q\ & (((\dbg_port_inst|hex_reader_inst|expect_leading_space~q\ & !\dbg_port_inst|hex_reader_inst|expect_leading_space~2_combout\)))) # 
-- (!\dbg_port_inst|hex_reader_inst|state.IDLE~q\ & ((\dbg_port_inst|hex_reader_start~q\) # ((\dbg_port_inst|hex_reader_inst|expect_leading_space~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001011110010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_start~q\,
	datab => \dbg_port_inst|hex_reader_inst|state.IDLE~q\,
	datac => \dbg_port_inst|hex_reader_inst|expect_leading_space~q\,
	datad => \dbg_port_inst|hex_reader_inst|expect_leading_space~2_combout\,
	combout => \dbg_port_inst|hex_reader_inst|expect_leading_space~3_combout\);

-- Location: FF_X47_Y44_N5
\dbg_port_inst|hex_reader_inst|expect_leading_space\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|expect_leading_space~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|expect_leading_space~q\);

-- Location: LCCOMB_X47_Y44_N30
\dbg_port_inst|hex_reader_inst|Selector1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector1~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & ((\dbg_port_inst|hex_reader_inst|process_0~10_combout\ & ((\dbg_port_inst|hex_reader_inst|expect_leading_space~q\))) # 
-- (!\dbg_port_inst|hex_reader_inst|process_0~10_combout\ & (!\dbg_port_inst|hex_reader_inst|state~22_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state~22_combout\,
	datab => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|expect_leading_space~q\,
	datad => \dbg_port_inst|hex_reader_inst|process_0~10_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector1~0_combout\);

-- Location: LCCOMB_X47_Y43_N24
\dbg_port_inst|hex_reader_inst|Selector1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector1~1_combout\ = (\dbg_port_inst|hex_reader_inst|Selector1~0_combout\) # (((\dbg_port_inst|hex_reader_inst|state.READ_CHAR~q\ & !\dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\)) # 
-- (!\dbg_port_inst|hex_reader_inst|value[1]~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101111111011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|Selector1~0_combout\,
	datab => \dbg_port_inst|hex_reader_inst|value[1]~0_combout\,
	datac => \dbg_port_inst|hex_reader_inst|state.READ_CHAR~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector1~1_combout\);

-- Location: FF_X47_Y43_N25
\dbg_port_inst|hex_reader_inst|state.READ_CHAR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector1~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|state.READ_CHAR~q\);

-- Location: LCCOMB_X47_Y43_N30
\dbg_port_inst|hex_reader_inst|rx_rd~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|rx_rd~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.READ_CHAR~q\ & \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|state.READ_CHAR~q\,
	datad => \dbg_port_inst|serial_port_inst|receiver_fifo|empty_int~q\,
	combout => \dbg_port_inst|hex_reader_inst|rx_rd~0_combout\);

-- Location: FF_X47_Y43_N31
\dbg_port_inst|hex_reader_inst|rx_rd\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|rx_rd~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|rx_rd~q\);

-- Location: FF_X47_Y43_N1
\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|rx_rd~q\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\);

-- Location: LCCOMB_X47_Y44_N6
\dbg_port_inst|hex_reader_inst|Selector4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector4~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & (!\dbg_port_inst|hex_reader_inst|expect_leading_space~q\ & \dbg_port_inst|hex_reader_inst|process_0~10_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|expect_leading_space~q\,
	datad => \dbg_port_inst|hex_reader_inst|process_0~10_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector4~0_combout\);

-- Location: FF_X47_Y44_N7
\dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector4~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH~q\);

-- Location: LCCOMB_X47_Y44_N28
\dbg_port_inst|hex_reader_inst|Selector6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector6~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH~q\ & !\dbg_port_inst|hex_reader_inst|Selector7~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.CHECK_LENGTH~q\,
	datad => \dbg_port_inst|hex_reader_inst|Selector7~0_combout\,
	combout => \dbg_port_inst|hex_reader_inst|Selector6~0_combout\);

-- Location: FF_X47_Y44_N29
\dbg_port_inst|hex_reader_inst|state.COMPLETE_DONE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector6~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|state.COMPLETE_DONE~q\);

-- Location: FF_X45_Y48_N13
\dbg_port_inst|hex_reader_inst|done\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|state.COMPLETE_DONE~q\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|done~q\);

-- Location: LCCOMB_X45_Y48_N8
\dbg_port_inst|Selector11~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector11~3_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & (!\dbg_port_inst|fsm_state~32_combout\ & \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datac => \dbg_port_inst|fsm_state~32_combout\,
	datad => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\,
	combout => \dbg_port_inst|Selector11~3_combout\);

-- Location: FF_X45_Y48_N9
\dbg_port_inst|fsm_state.PRINT_OK\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector11~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|fsm_state.PRINT_OK~q\);

-- Location: LCCOMB_X45_Y48_N26
\dbg_port_inst|fsm_state~33\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|fsm_state~33_combout\ = (\dbg_port_inst|fsm_state.PRINT_OK~q\) # (\dbg_port_inst|fsm_state.PRINT_ERROR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.PRINT_OK~q\,
	datac => \dbg_port_inst|fsm_state.PRINT_ERROR~q\,
	combout => \dbg_port_inst|fsm_state~33_combout\);

-- Location: FF_X45_Y48_N27
\dbg_port_inst|str_writer_start\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|fsm_state~33_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_start~q\);

-- Location: LCCOMB_X39_Y48_N8
\dbg_port_inst|str_writer_inst|Selector1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Selector1~0_combout\ = (\dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\ & ((\dbg_port_inst|str_writer_inst|tx_wr~q\) # ((\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\) # 
-- (\dbg_port_inst|str_writer_inst|state~8_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|tx_wr~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datac => \dbg_port_inst|str_writer_inst|state~8_combout\,
	datad => \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\,
	combout => \dbg_port_inst|str_writer_inst|Selector1~0_combout\);

-- Location: LCCOMB_X39_Y48_N16
\dbg_port_inst|str_writer_inst|Selector1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Selector1~1_combout\ = (\dbg_port_inst|str_writer_inst|Selector1~0_combout\) # ((\dbg_port_inst|str_writer_start~q\ & !\dbg_port_inst|str_writer_inst|state.IDLE~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|str_writer_start~q\,
	datac => \dbg_port_inst|str_writer_inst|Selector1~0_combout\,
	datad => \dbg_port_inst|str_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|str_writer_inst|Selector1~1_combout\);

-- Location: FF_X39_Y48_N17
\dbg_port_inst|str_writer_inst|state.WRITE_CHAR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Selector1~1_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\);

-- Location: LCCOMB_X39_Y48_N18
\dbg_port_inst|str_writer_inst|tx_wr~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|tx_wr~0_combout\ = (!\dbg_port_inst|str_writer_inst|tx_wr~q\ & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ & \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|tx_wr~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datad => \dbg_port_inst|str_writer_inst|state.WRITE_CHAR~q\,
	combout => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\);

-- Location: LCCOMB_X38_Y48_N8
\dbg_port_inst|str_writer_inst|tx_wr~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|tx_wr~feeder_combout\ = \dbg_port_inst|str_writer_inst|tx_wr~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	combout => \dbg_port_inst|str_writer_inst|tx_wr~feeder_combout\);

-- Location: FF_X38_Y48_N9
\dbg_port_inst|str_writer_inst|tx_wr\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|tx_wr~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|tx_wr~q\);

-- Location: LCCOMB_X39_Y47_N20
\dbg_port_inst|ci_hex_writer_inst|tx_wr~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\ = (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ & ((\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\) # (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\);

-- Location: FF_X38_Y48_N27
\dbg_port_inst|ci_hex_writer_inst|tx_wr\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\);

-- Location: LCCOMB_X38_Y48_N28
\dbg_port_inst|uart_tx_wr\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_wr~combout\ = (\dbg_port_inst|str_writer_inst|tx_wr~q\) # (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|str_writer_inst|tx_wr~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|uart_tx_wr~combout\);

-- Location: LCCOMB_X38_Y45_N12
\dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~2_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~1_combout\ & ((\dbg_port_inst|uart_tx_wr~combout\) # 
-- ((!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\ & \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\)))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~1_combout\ & 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~1_combout\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datad => \dbg_port_inst|uart_tx_wr~combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~2_combout\);

-- Location: FF_X38_Y45_N13
\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_next~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\);

-- Location: LCCOMB_X38_Y45_N22
\dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\ = (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ & ((\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\) # (\dbg_port_inst|str_writer_inst|tx_wr~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010001010100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	datac => \dbg_port_inst|str_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\);

-- Location: FF_X38_Y46_N5
\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0));

-- Location: LCCOMB_X38_Y46_N10
\dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~0_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) $ (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~0_combout\);

-- Location: FF_X38_Y46_N11
\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add1~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1));

-- Location: LCCOMB_X38_Y46_N24
\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~2_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1) $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1))))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1) $ (\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000011010010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(1),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~2_combout\);

-- Location: LCCOMB_X38_Y46_N30
\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~3_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~2_combout\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\ $ 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~2_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~3_combout\);

-- Location: LCCOMB_X38_Y45_N18
\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~4_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~3_combout\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3) $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~3_combout\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~4_combout\);

-- Location: LCCOMB_X38_Y45_N28
\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~5_combout\ = (\dbg_port_inst|str_writer_inst|tx_wr~q\) # ((\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\) # ((!\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~4_combout\ & 
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111011100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~4_combout\,
	datab => \dbg_port_inst|str_writer_inst|tx_wr~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~5_combout\);

-- Location: FF_X38_Y45_N29
\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_next~5_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\);

-- Location: LCCOMB_X39_Y45_N2
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector0~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\) # ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\ & 
-- ((!\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector0~0_combout\);

-- Location: FF_X39_Y45_N3
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\);

-- Location: LCCOMB_X39_Y45_N0
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector1~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\ & (((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\ & 
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\)) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector1~0_combout\);

-- Location: FF_X39_Y45_N1
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector1~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\);

-- Location: LCCOMB_X38_Y45_N0
\dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\) # ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\) # 
-- ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\) # (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\);

-- Location: FF_X39_Y45_N11
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~9_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(0));

-- Location: LCCOMB_X39_Y45_N12
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~11_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(1) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~10\)) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(1) & ((\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~10\) # (GND)))
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~12\ = CARRY((!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~10\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(1),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[0]~10\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~11_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~12\);

-- Location: FF_X39_Y45_N13
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~11_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(1));

-- Location: LCCOMB_X39_Y45_N14
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~13_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(2) & (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~12\ $ (GND))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(2) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~12\ & VCC))
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~14\ = CARRY((\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(2) & !\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~12\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(2),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[1]~12\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~13_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~14\);

-- Location: FF_X39_Y45_N15
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~13_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(2));

-- Location: LCCOMB_X39_Y45_N16
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~15_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(3) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~14\)) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(3) & ((\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~14\) # (GND)))
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~16\ = CARRY((!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~14\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(3),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[2]~14\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~15_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~16\);

-- Location: FF_X39_Y45_N17
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~15_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(3));

-- Location: LCCOMB_X39_Y45_N18
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~17_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(4) & (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~16\ $ (GND))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(4) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~16\ & VCC))
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~18\ = CARRY((\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(4) & !\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~16\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(4),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[3]~16\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~17_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~18\);

-- Location: FF_X39_Y45_N19
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~17_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(4));

-- Location: LCCOMB_X39_Y45_N20
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~19\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~19_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(5) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~18\)) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(5) & ((\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~18\) # (GND)))
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~20\ = CARRY((!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~18\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(5),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[4]~18\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~19_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~20\);

-- Location: FF_X39_Y45_N21
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~19_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(5));

-- Location: LCCOMB_X39_Y45_N22
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~21\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~21_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(6) & (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~20\ $ (GND))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(6) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~20\ & VCC))
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~22\ = CARRY((\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(6) & !\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~20\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(6),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[5]~20\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~21_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~22\);

-- Location: FF_X39_Y45_N23
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~21_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(6));

-- Location: LCCOMB_X39_Y45_N24
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~23_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(7) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~22\)) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(7) & ((\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~22\) # (GND)))
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~24\ = CARRY((!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~22\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(7),
	datad => VCC,
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[6]~22\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~23_combout\,
	cout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~24\);

-- Location: FF_X39_Y45_N25
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~23_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(7));

-- Location: LCCOMB_X39_Y45_N8
\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(7) & (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(4) & 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(6) & \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(7),
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(4),
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(6),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(5),
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1_combout\);

-- Location: LCCOMB_X39_Y45_N26
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[8]~25\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[8]~25_combout\ = \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(8) $ (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~24\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010110100101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(8),
	cin => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[7]~24\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[8]~25_combout\);

-- Location: FF_X39_Y45_N27
\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt[8]~25_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|serial_port_inst|transmitter_inst|WideOr0~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(8));

-- Location: LCCOMB_X39_Y45_N6
\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0_combout\ = (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(1) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(3) & 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(2) & !\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(1),
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(3),
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(2),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0_combout\);

-- Location: LCCOMB_X39_Y45_N4
\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1_combout\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(8) & 
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(8),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\);

-- Location: LCCOMB_X39_Y45_N30
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector2~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector2~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\) # ((!\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\ & 
-- \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.SEND_START_BIT~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.SEND_START_BIT~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector2~0_combout\);

-- Location: FF_X39_Y45_N31
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.SEND_START_BIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector2~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.SEND_START_BIT~q\);

-- Location: LCCOMB_X39_Y45_N28
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector3~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.SEND_START_BIT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1_combout\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(8) & \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.SEND_START_BIT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~1_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|clk_cnt\(8),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector3~0_combout\);

-- Location: FF_X39_Y45_N29
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector3~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\);

-- Location: LCCOMB_X38_Y45_N24
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector4~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\) # ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\) # 
-- ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\ & !\dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111011111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector4~0_combout\);

-- Location: FF_X38_Y45_N25
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector4~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\);

-- Location: LCCOMB_X38_Y45_N14
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2) & (!\dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\ & 
-- ((!\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\)))) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2) & 
-- (((!\dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000011101110111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|bit_cnt\(2),
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|LessThan0~0_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|empty_int~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~0_combout\);

-- Location: LCCOMB_X38_Y45_N10
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~1_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~0_combout\ & 
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~0_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~1_combout\);

-- Location: FF_X38_Y45_N11
\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector5~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\);

-- Location: LCCOMB_X39_Y46_N30
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\);

-- Location: FF_X39_Y46_N31
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[12]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(12));

-- Location: LCCOMB_X39_Y48_N24
\dbg_port_inst|Selector20~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector20~0_combout\ = (\dbg_port_inst|fsm_state.PRINT_OK~q\) # ((\dbg_port_inst|str_writer_str[0][1]~q\ & !\dbg_port_inst|fsm_state.PRINT_ERROR~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|fsm_state.PRINT_OK~q\,
	datac => \dbg_port_inst|str_writer_str[0][1]~q\,
	datad => \dbg_port_inst|fsm_state.PRINT_ERROR~q\,
	combout => \dbg_port_inst|Selector20~0_combout\);

-- Location: FF_X39_Y48_N25
\dbg_port_inst|str_writer_str[0][1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|Selector20~0_combout\,
	ena => \res_n~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_str[0][1]~q\);

-- Location: LCCOMB_X38_Y48_N6
\dbg_port_inst|str_writer_inst|Mux6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux6~0_combout\ = (\dbg_port_inst|str_writer_inst|idx\(1) & (((\dbg_port_inst|str_writer_str[1][4]~q\) # (!\dbg_port_inst|str_writer_inst|idx\(0))))) # (!\dbg_port_inst|str_writer_inst|idx\(1) & 
-- ((\dbg_port_inst|str_writer_str[0][1]~q\) # ((\dbg_port_inst|str_writer_inst|idx\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010111101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datab => \dbg_port_inst|str_writer_str[0][1]~q\,
	datac => \dbg_port_inst|str_writer_str[1][4]~q\,
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Mux6~0_combout\);

-- Location: LCCOMB_X38_Y48_N0
\dbg_port_inst|str_writer_inst|Mux6~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux6~1_combout\ = (\dbg_port_inst|str_writer_inst|idx\(2) & (!\dbg_port_inst|str_writer_inst|idx\(1) & (\dbg_port_inst|str_writer_str[1][4]~q\))) # (!\dbg_port_inst|str_writer_inst|idx\(2) & 
-- (((\dbg_port_inst|str_writer_inst|Mux6~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100111101000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datab => \dbg_port_inst|str_writer_str[1][4]~q\,
	datac => \dbg_port_inst|str_writer_inst|idx\(2),
	datad => \dbg_port_inst|str_writer_inst|Mux6~0_combout\,
	combout => \dbg_port_inst|str_writer_inst|Mux6~1_combout\);

-- Location: FF_X38_Y48_N1
\dbg_port_inst|str_writer_inst|tx_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Mux6~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|tx_data\(1));

-- Location: LCCOMB_X39_Y47_N26
\dbg_port_inst|ci_hex_writer_inst|Selector66~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector66~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\) # ((\dbg_port_inst|hex_writer_width\(1)) # (!\dbg_port_inst|hex_writer_width\(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111110101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|hex_writer_width\(0),
	datad => \dbg_port_inst|hex_writer_width\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector66~0_combout\);

-- Location: LCCOMB_X41_Y48_N24
\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (((!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & \dbg_port_inst|hex_writer_start~q\)) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\))) # (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|hex_writer_start~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011101100001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datad => \dbg_port_inst|hex_writer_start~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0_combout\);

-- Location: FF_X39_Y47_N27
\dbg_port_inst|ci_hex_writer_inst|first_digit_mask[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector66~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(1));

-- Location: LCCOMB_X41_Y47_N8
\dbg_port_inst|ci_hex_writer_inst|Selector65~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector65~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\) # (\dbg_port_inst|hex_writer_width\(0) $ (!\dbg_port_inst|hex_writer_width\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011110101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_width\(0),
	datac => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|hex_writer_width\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector65~0_combout\);

-- Location: LCCOMB_X41_Y48_N8
\dbg_port_inst|ci_hex_writer_inst|first_digit_mask~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|first_digit_mask~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\))) # 
-- (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (((\dbg_port_inst|hex_writer_start~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011101100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datad => \dbg_port_inst|hex_writer_start~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask~0_combout\);

-- Location: FF_X41_Y47_N9
\dbg_port_inst|ci_hex_writer_inst|first_digit_mask[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector65~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(2));

-- Location: IOIBUF_X0_Y52_N22
\hex2[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex2(6),
	o => \hex2[6]~input_o\);

-- Location: LCCOMB_X40_Y48_N28
\dbg_port_inst|Equal0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Equal0~2_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(2) & (!\dbg_port_inst|hex_reader_inst|value\(3) & (!\dbg_port_inst|hex_reader_inst|value\(0) & !\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(3),
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|Equal0~2_combout\);

-- Location: LCCOMB_X32_Y53_N8
\dbg_port_inst|hex_writer_value~27\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~27_combout\ = (\hex2[6]~input_o\ & !\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex2[6]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~27_combout\);

-- Location: LCCOMB_X40_Y48_N22
\dbg_port_inst|hex_writer_value[22]~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[22]~17_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3)) # ((\dbg_port_inst|hex_reader_inst|value\(0)) # (\dbg_port_inst|hex_reader_inst|value\(2) $ (\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(3),
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_value[22]~17_combout\);

-- Location: LCCOMB_X40_Y48_N26
\dbg_port_inst|hex_writer_value[28]~90\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[28]~90_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & (!\dbg_port_inst|hex_writer_value[22]~17_combout\ & \res_n~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datab => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datac => \dbg_port_inst|hex_writer_value[22]~17_combout\,
	datad => \res_n~input_o\,
	combout => \dbg_port_inst|hex_writer_value[28]~90_combout\);

-- Location: FF_X32_Y53_N9
\dbg_port_inst|hex_writer_value[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~27_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(22));

-- Location: IOIBUF_X0_Y55_N15
\hex2[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex2(2),
	o => \hex2[2]~input_o\);

-- Location: LCCOMB_X32_Y53_N4
\dbg_port_inst|hex_writer_value~33\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~33_combout\ = (\hex2[2]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex2[2]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~33_combout\);

-- Location: FF_X32_Y53_N5
\dbg_port_inst|hex_writer_value[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~33_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(18));

-- Location: IOIBUF_X0_Y42_N8
\hex0[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex0(6),
	o => \hex0[6]~input_o\);

-- Location: LCCOMB_X43_Y45_N26
\dbg_port_inst|hex_reader_inst|Selector28~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector28~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector28~0_combout\);

-- Location: FF_X43_Y45_N27
\dbg_port_inst|hex_reader_inst|value[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector28~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(6));

-- Location: LCCOMB_X45_Y48_N10
\dbg_port_inst|Equal13~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Equal13~0_combout\ = (!\dbg_port_inst|write_address\(3) & \dbg_port_inst|write_address\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|write_address\(3),
	datad => \dbg_port_inst|write_address\(1),
	combout => \dbg_port_inst|Equal13~0_combout\);

-- Location: LCCOMB_X43_Y48_N10
\dbg_port_inst|Selector11~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Selector11~2_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|done~q\,
	datad => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\,
	combout => \dbg_port_inst|Selector11~2_combout\);

-- Location: LCCOMB_X43_Y49_N6
\dbg_port_inst|switches[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|switches[0]~0_combout\ = (\dbg_port_inst|Equal13~0_combout\ & (!\dbg_port_inst|write_address\(2) & (!\dbg_port_inst|write_address\(0) & \dbg_port_inst|Selector11~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Equal13~0_combout\,
	datab => \dbg_port_inst|write_address\(2),
	datac => \dbg_port_inst|write_address\(0),
	datad => \dbg_port_inst|Selector11~2_combout\,
	combout => \dbg_port_inst|switches[0]~0_combout\);

-- Location: FF_X43_Y46_N11
\dbg_port_inst|switches[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(6));

-- Location: IOIBUF_X42_Y0_N22
\ledr[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(6),
	o => \ledr[6]~input_o\);

-- Location: LCCOMB_X43_Y46_N24
\dbg_port_inst|hex_writer_value[6]~54\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[6]~54_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3)) # ((\dbg_port_inst|hex_reader_inst|value\(2) & \dbg_port_inst|hex_reader_inst|value\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(3),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_value[6]~54_combout\);

-- Location: LCCOMB_X43_Y46_N14
\dbg_port_inst|hex_writer_value[6]~53\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[6]~53_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3)) # ((\dbg_port_inst|hex_reader_inst|value\(2) & !\dbg_port_inst|hex_reader_inst|value\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(3),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_value[6]~53_combout\);

-- Location: LCCOMB_X45_Y48_N16
\dbg_port_inst|Equal18~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Equal18~0_combout\ = (\dbg_port_inst|write_address\(3) & (\dbg_port_inst|write_address\(2) & (!\dbg_port_inst|write_address\(1) & !\dbg_port_inst|write_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|write_address\(3),
	datab => \dbg_port_inst|write_address\(2),
	datac => \dbg_port_inst|write_address\(1),
	datad => \dbg_port_inst|write_address\(0),
	combout => \dbg_port_inst|Equal18~0_combout\);

-- Location: LCCOMB_X45_Y48_N14
\dbg_port_inst|nes_buttons_intern[4]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[4]~2_combout\ = (\dbg_port_inst|Equal18~0_combout\ & (\dbg_port_inst|hex_reader_inst|done~q\ & \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Equal18~0_combout\,
	datac => \dbg_port_inst|hex_reader_inst|done~q\,
	datad => \dbg_port_inst|fsm_state.WRITE_OPERATION_READ_DATA~q\,
	combout => \dbg_port_inst|nes_buttons_intern[4]~2_combout\);

-- Location: FF_X43_Y46_N17
\dbg_port_inst|nes_buttons_intern[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(6));

-- Location: LCCOMB_X43_Y46_N6
\dbg_port_inst|hex_writer_value~66\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~66_combout\ = (\dbg_port_inst|hex_writer_value[6]~54_combout\ & (((\dbg_port_inst|hex_writer_value[6]~53_combout\ & \dbg_port_inst|nes_buttons_intern\(6))))) # (!\dbg_port_inst|hex_writer_value[6]~54_combout\ & 
-- ((\ledr[6]~input_o\) # ((!\dbg_port_inst|hex_writer_value[6]~53_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110001100100011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ledr[6]~input_o\,
	datab => \dbg_port_inst|hex_writer_value[6]~54_combout\,
	datac => \dbg_port_inst|hex_writer_value[6]~53_combout\,
	datad => \dbg_port_inst|nes_buttons_intern\(6),
	combout => \dbg_port_inst|hex_writer_value~66_combout\);

-- Location: LCCOMB_X43_Y46_N10
\dbg_port_inst|hex_writer_value~67\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~67_combout\ = (\dbg_port_inst|hex_reader_max_length[0]~3_combout\ & ((\dbg_port_inst|hex_writer_value~66_combout\ & ((\dbg_port_inst|switches\(6)))) # (!\dbg_port_inst|hex_writer_value~66_combout\ & (\hex0[6]~input_o\)))) # 
-- (!\dbg_port_inst|hex_reader_max_length[0]~3_combout\ & (((\dbg_port_inst|hex_writer_value~66_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \hex0[6]~input_o\,
	datab => \dbg_port_inst|hex_reader_max_length[0]~3_combout\,
	datac => \dbg_port_inst|switches\(6),
	datad => \dbg_port_inst|hex_writer_value~66_combout\,
	combout => \dbg_port_inst|hex_writer_value~67_combout\);

-- Location: LCCOMB_X39_Y49_N28
\dbg_port_inst|hex_writer_value[6]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[6]~feeder_combout\ = \dbg_port_inst|hex_writer_value~67_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value~67_combout\,
	combout => \dbg_port_inst|hex_writer_value[6]~feeder_combout\);

-- Location: IOIBUF_X16_Y73_N1
\ledg[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(6),
	o => \ledg[6]~input_o\);

-- Location: LCCOMB_X40_Y46_N26
\dbg_port_inst|hex_writer_value[4]~57\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[4]~57_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(1) & \dbg_port_inst|hex_reader_inst|value\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_writer_value[4]~57_combout\);

-- Location: LCCOMB_X40_Y48_N6
\dbg_port_inst|hex_writer_value[60]~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[60]~14_combout\ = (\res_n~input_o\ & (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & \dbg_port_inst|hex_reader_inst|done~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \res_n~input_o\,
	datac => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datad => \dbg_port_inst|hex_reader_inst|done~q\,
	combout => \dbg_port_inst|hex_writer_value[60]~14_combout\);

-- Location: LCCOMB_X40_Y46_N20
\dbg_port_inst|hex_writer_value[4]~58\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[4]~58_combout\ = (\dbg_port_inst|hex_writer_value[60]~14_combout\ & ((\dbg_port_inst|hex_reader_inst|value\(3) & (!\dbg_port_inst|hex_reader_inst|value\(0) & \dbg_port_inst|hex_writer_value[4]~57_combout\)) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(3) & ((\dbg_port_inst|hex_writer_value[4]~57_combout\) # (!\dbg_port_inst|hex_reader_inst|value\(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_writer_value[4]~57_combout\,
	datad => \dbg_port_inst|hex_writer_value[60]~14_combout\,
	combout => \dbg_port_inst|hex_writer_value[4]~58_combout\);

-- Location: FF_X39_Y49_N29
\dbg_port_inst|hex_writer_value[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[6]~feeder_combout\,
	asdata => \ledg[6]~input_o\,
	sload => \dbg_port_inst|hex_reader_inst|value\(0),
	ena => \dbg_port_inst|hex_writer_value[4]~58_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(6));

-- Location: LCCOMB_X42_Y46_N20
\dbg_port_inst|keys[2]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|keys[2]~3_combout\ = !\dbg_port_inst|hex_reader_inst|value\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|keys[2]~3_combout\);

-- Location: LCCOMB_X43_Y49_N20
\dbg_port_inst|keys[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|keys[0]~0_combout\ = (\dbg_port_inst|Equal13~0_combout\ & (!\dbg_port_inst|write_address\(2) & (\dbg_port_inst|write_address\(0) & \dbg_port_inst|Selector11~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Equal13~0_combout\,
	datab => \dbg_port_inst|write_address\(2),
	datac => \dbg_port_inst|write_address\(0),
	datad => \dbg_port_inst|Selector11~2_combout\,
	combout => \dbg_port_inst|keys[0]~0_combout\);

-- Location: FF_X42_Y46_N21
\dbg_port_inst|keys[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|keys[2]~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|keys[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|keys\(2));

-- Location: IOIBUF_X69_Y73_N22
\ledr[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(2),
	o => \ledr[2]~input_o\);

-- Location: IOIBUF_X38_Y73_N15
\ledg[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(2),
	o => \ledg[2]~input_o\);

-- Location: LCCOMB_X41_Y49_N30
\dbg_port_inst|hex_writer_value[2]~77\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[2]~77_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0)) # ((!\dbg_port_inst|hex_reader_inst|value\(1) & \dbg_port_inst|hex_reader_inst|value\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_writer_value[2]~77_combout\);

-- Location: LCCOMB_X41_Y49_N16
\dbg_port_inst|hex_writer_value[2]~78\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[2]~78_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0)) # ((\dbg_port_inst|hex_reader_inst|value\(1) & \dbg_port_inst|hex_reader_inst|value\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|hex_writer_value[2]~78_combout\);

-- Location: LCCOMB_X41_Y49_N26
\dbg_port_inst|hex_writer_value~86\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~86_combout\ = (\dbg_port_inst|hex_writer_value[2]~77_combout\ & ((\dbg_port_inst|hex_writer_value[2]~78_combout\ & ((\ledg[2]~input_o\))) # (!\dbg_port_inst|hex_writer_value[2]~78_combout\ & (\ledr[2]~input_o\)))) # 
-- (!\dbg_port_inst|hex_writer_value[2]~77_combout\ & (((!\dbg_port_inst|hex_writer_value[2]~78_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000010101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ledr[2]~input_o\,
	datab => \ledg[2]~input_o\,
	datac => \dbg_port_inst|hex_writer_value[2]~77_combout\,
	datad => \dbg_port_inst|hex_writer_value[2]~78_combout\,
	combout => \dbg_port_inst|hex_writer_value~86_combout\);

-- Location: IOIBUF_X0_Y49_N1
\hex0[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex0(2),
	o => \hex0[2]~input_o\);

-- Location: FF_X41_Y49_N13
\dbg_port_inst|switches[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(2));

-- Location: LCCOMB_X41_Y49_N12
\dbg_port_inst|hex_writer_value~87\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~87_combout\ = (\dbg_port_inst|hex_writer_value~86_combout\ & (((\dbg_port_inst|switches\(2)) # (!\dbg_port_inst|Selector13~0_combout\)))) # (!\dbg_port_inst|hex_writer_value~86_combout\ & (\hex0[2]~input_o\ & 
-- ((\dbg_port_inst|Selector13~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value~86_combout\,
	datab => \hex0[2]~input_o\,
	datac => \dbg_port_inst|switches\(2),
	datad => \dbg_port_inst|Selector13~0_combout\,
	combout => \dbg_port_inst|hex_writer_value~87_combout\);

-- Location: LCCOMB_X41_Y49_N4
\dbg_port_inst|hex_writer_value~88\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~88_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(1) & (!\dbg_port_inst|keys\(2))) # (!\dbg_port_inst|hex_reader_inst|value\(1) & 
-- ((\dbg_port_inst|hex_writer_value~87_combout\))))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & (((\dbg_port_inst|hex_writer_value~87_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111101000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|keys\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_writer_value~87_combout\,
	combout => \dbg_port_inst|hex_writer_value~88_combout\);

-- Location: LCCOMB_X40_Y49_N20
\dbg_port_inst|hex_writer_value[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[2]~feeder_combout\ = \dbg_port_inst|hex_writer_value~88_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_writer_value~88_combout\,
	combout => \dbg_port_inst|hex_writer_value[2]~feeder_combout\);

-- Location: LCCOMB_X43_Y46_N18
\dbg_port_inst|nes_buttons_intern[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[2]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|nes_buttons_intern[2]~feeder_combout\);

-- Location: FF_X43_Y46_N19
\dbg_port_inst|nes_buttons_intern[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes_buttons_intern[2]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(2));

-- Location: LCCOMB_X40_Y48_N4
\dbg_port_inst|hex_writer_value[3]~82\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[3]~82_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & (\dbg_port_inst|hex_reader_inst|value\(2) & (!\dbg_port_inst|hex_reader_inst|value\(0) & !\dbg_port_inst|hex_reader_inst|value\(1)))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(3) & ((\dbg_port_inst|hex_reader_inst|value\(2) $ (\dbg_port_inst|hex_reader_inst|value\(1))) # (!\dbg_port_inst|hex_reader_inst|value\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001001100101011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(3),
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_value[3]~82_combout\);

-- Location: LCCOMB_X40_Y48_N12
\dbg_port_inst|hex_writer_value[3]~94\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[3]~94_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & (\dbg_port_inst|hex_writer_value[3]~82_combout\ & \res_n~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datab => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datac => \dbg_port_inst|hex_writer_value[3]~82_combout\,
	datad => \res_n~input_o\,
	combout => \dbg_port_inst|hex_writer_value[3]~94_combout\);

-- Location: FF_X40_Y49_N21
\dbg_port_inst|hex_writer_value[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[2]~feeder_combout\,
	asdata => \dbg_port_inst|nes_buttons_intern\(2),
	sload => \dbg_port_inst|hex_reader_inst|value\(3),
	ena => \dbg_port_inst|hex_writer_value[3]~94_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(2));

-- Location: LCCOMB_X40_Y49_N14
\dbg_port_inst|ci_hex_writer_inst|Selector61~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector61~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & ((\dbg_port_inst|hex_writer_value\(2)) # (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(2),
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector61~0_combout\);

-- Location: LCCOMB_X41_Y48_N4
\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0_combout\) # ((!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\ & \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~0_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\);

-- Location: FF_X40_Y49_N15
\dbg_port_inst|ci_hex_writer_inst|value_buffer[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector61~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(2));

-- Location: LCCOMB_X39_Y49_N20
\dbg_port_inst|ci_hex_writer_inst|Selector57~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector57~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(2)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(6)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(6),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(2),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector57~0_combout\);

-- Location: FF_X39_Y49_N21
\dbg_port_inst|ci_hex_writer_inst|value_buffer[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector57~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(6));

-- Location: LCCOMB_X43_Y45_N18
\dbg_port_inst|hex_reader_inst|Selector24~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector24~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & \dbg_port_inst|hex_reader_inst|value\(6))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|value\(6),
	combout => \dbg_port_inst|hex_reader_inst|Selector24~0_combout\);

-- Location: FF_X43_Y45_N19
\dbg_port_inst|hex_reader_inst|value[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector24~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(10));

-- Location: FF_X43_Y49_N31
\dbg_port_inst|switches[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(10),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(10));

-- Location: IOIBUF_X62_Y73_N15
\hex1[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex1(2),
	o => \hex1[2]~input_o\);

-- Location: LCCOMB_X43_Y49_N30
\dbg_port_inst|hex_writer_value~51\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~51_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (\dbg_port_inst|hex_reader_inst|value\(1) & ((\hex1[2]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(10))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100101010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|switches\(10),
	datad => \hex1[2]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~51_combout\);

-- Location: IOIBUF_X65_Y73_N8
\ledr[10]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(10),
	o => \ledr[10]~input_o\);

-- Location: LCCOMB_X42_Y49_N22
\dbg_port_inst|hex_writer_value~52\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~52_combout\ = (\dbg_port_inst|hex_writer_value~51_combout\) # ((!\dbg_port_inst|hex_reader_inst|value\(1) & \ledr[10]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|hex_writer_value~51_combout\,
	datad => \ledr[10]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~52_combout\);

-- Location: LCCOMB_X40_Y46_N12
\dbg_port_inst|hex_writer_value[16]~30\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[16]~30_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(3) & !\dbg_port_inst|hex_reader_inst|value\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|value\(3),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|hex_writer_value[16]~30_combout\);

-- Location: LCCOMB_X38_Y49_N24
\dbg_port_inst|hex_writer_value[16]~91\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[16]~91_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & (\dbg_port_inst|hex_writer_value[16]~30_combout\ & (\res_n~input_o\ & \dbg_port_inst|fsm_state.READ_OPERATION~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datab => \dbg_port_inst|hex_writer_value[16]~30_combout\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	combout => \dbg_port_inst|hex_writer_value[16]~91_combout\);

-- Location: FF_X42_Y49_N23
\dbg_port_inst|hex_writer_value[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~52_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(10));

-- Location: LCCOMB_X39_Y49_N16
\dbg_port_inst|ci_hex_writer_inst|Selector53~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector53~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(6))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(10))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(6),
	datac => \dbg_port_inst|hex_writer_value\(10),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector53~0_combout\);

-- Location: FF_X39_Y49_N17
\dbg_port_inst|ci_hex_writer_inst|value_buffer[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector53~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(10));

-- Location: IOIBUF_X0_Y33_N15
\ledr[14]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(14),
	o => \ledr[14]~input_o\);

-- Location: IOIBUF_X38_Y73_N22
\hex1[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex1(6),
	o => \hex1[6]~input_o\);

-- Location: LCCOMB_X42_Y49_N24
\dbg_port_inst|hex_writer_value~40\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~40_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & ((\dbg_port_inst|hex_reader_inst|value\(1) & ((\hex1[6]~input_o\))) # (!\dbg_port_inst|hex_reader_inst|value\(1) & (\ledr[14]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datab => \ledr[14]~input_o\,
	datac => \dbg_port_inst|hex_reader_inst|value\(2),
	datad => \hex1[6]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~40_combout\);

-- Location: LCCOMB_X43_Y45_N10
\dbg_port_inst|hex_reader_inst|Selector20~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector20~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(10) & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(10),
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector20~0_combout\);

-- Location: FF_X43_Y45_N11
\dbg_port_inst|hex_reader_inst|value[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector20~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(14));

-- Location: LCCOMB_X41_Y49_N0
\dbg_port_inst|switches[14]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|switches[14]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(14)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(14),
	combout => \dbg_port_inst|switches[14]~feeder_combout\);

-- Location: FF_X41_Y49_N1
\dbg_port_inst|switches[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|switches[14]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(14));

-- Location: LCCOMB_X42_Y49_N8
\dbg_port_inst|hex_writer_value~93\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~93_combout\ = (\dbg_port_inst|hex_writer_value~40_combout\) # ((\dbg_port_inst|hex_reader_inst|value\(1) & (!\dbg_port_inst|hex_reader_inst|value\(2) & \dbg_port_inst|switches\(14))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datab => \dbg_port_inst|hex_writer_value~40_combout\,
	datac => \dbg_port_inst|hex_reader_inst|value\(2),
	datad => \dbg_port_inst|switches\(14),
	combout => \dbg_port_inst|hex_writer_value~93_combout\);

-- Location: FF_X42_Y49_N9
\dbg_port_inst|hex_writer_value[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~93_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(14));

-- Location: LCCOMB_X39_Y49_N4
\dbg_port_inst|ci_hex_writer_inst|Selector49~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector49~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(10))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(14))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(10),
	datac => \dbg_port_inst|hex_writer_value\(14),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector49~0_combout\);

-- Location: FF_X39_Y49_N5
\dbg_port_inst|ci_hex_writer_inst|value_buffer[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector49~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(14));

-- Location: LCCOMB_X39_Y49_N22
\dbg_port_inst|ci_hex_writer_inst|Selector45~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector45~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(14)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(18)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(18),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(14),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector45~0_combout\);

-- Location: FF_X39_Y49_N23
\dbg_port_inst|ci_hex_writer_inst|value_buffer[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector45~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(18));

-- Location: LCCOMB_X39_Y49_N10
\dbg_port_inst|ci_hex_writer_inst|Selector41~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector41~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(18)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(22)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(22),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(18),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector41~0_combout\);

-- Location: FF_X39_Y49_N11
\dbg_port_inst|ci_hex_writer_inst|value_buffer[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector41~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(22));

-- Location: IOIBUF_X27_Y73_N22
\hex3[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex3(2),
	o => \hex3[2]~input_o\);

-- Location: LCCOMB_X32_Y53_N2
\dbg_port_inst|hex_writer_value~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~24_combout\ = (\hex3[2]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex3[2]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~24_combout\);

-- Location: FF_X32_Y53_N3
\dbg_port_inst|hex_writer_value[26]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~24_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(26));

-- Location: LCCOMB_X39_Y49_N24
\dbg_port_inst|ci_hex_writer_inst|Selector37~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector37~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(22))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(26))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(22),
	datac => \dbg_port_inst|hex_writer_value\(26),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector37~0_combout\);

-- Location: FF_X39_Y49_N25
\dbg_port_inst|ci_hex_writer_inst|value_buffer[26]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector37~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(26));

-- Location: IOIBUF_X27_Y73_N15
\hex3[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex3(6),
	o => \hex3[6]~input_o\);

-- Location: LCCOMB_X32_Y53_N16
\dbg_port_inst|hex_writer_value~20\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~20_combout\ = (\hex3[6]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex3[6]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~20_combout\);

-- Location: FF_X32_Y53_N17
\dbg_port_inst|hex_writer_value[30]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~20_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(30));

-- Location: LCCOMB_X39_Y49_N6
\dbg_port_inst|ci_hex_writer_inst|Selector33~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector33~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(26))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(30))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(26),
	datac => \dbg_port_inst|hex_writer_value\(30),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector33~0_combout\);

-- Location: FF_X39_Y49_N7
\dbg_port_inst|ci_hex_writer_inst|value_buffer[30]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector33~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(30));

-- Location: IOIBUF_X20_Y73_N8
\hex4[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex4(2),
	o => \hex4[2]~input_o\);

-- Location: LCCOMB_X40_Y48_N20
\dbg_port_inst|Equal0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Equal0~1_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (!\dbg_port_inst|hex_reader_inst|value\(3) & (!\dbg_port_inst|hex_reader_inst|value\(0) & \dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(3),
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|Equal0~1_combout\);

-- Location: LCCOMB_X40_Y48_N14
\dbg_port_inst|hex_writer_value[60]~89\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[60]~89_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & (\res_n~input_o\ & (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & \dbg_port_inst|Equal0~1_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datab => \res_n~input_o\,
	datac => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datad => \dbg_port_inst|Equal0~1_combout\,
	combout => \dbg_port_inst|hex_writer_value[60]~89_combout\);

-- Location: FF_X27_Y69_N15
\dbg_port_inst|hex_writer_value[34]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex4[2]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(34));

-- Location: LCCOMB_X27_Y69_N2
\dbg_port_inst|ci_hex_writer_inst|Selector29~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector29~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(30))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(34))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(30),
	datab => \dbg_port_inst|hex_writer_value\(34),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector29~0_combout\);

-- Location: FF_X27_Y69_N3
\dbg_port_inst|ci_hex_writer_inst|value_buffer[34]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector29~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(34));

-- Location: IOIBUF_X23_Y73_N15
\hex4[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex4(6),
	o => \hex4[6]~input_o\);

-- Location: FF_X27_Y69_N5
\dbg_port_inst|hex_writer_value[38]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex4[6]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(38));

-- Location: LCCOMB_X27_Y69_N30
\dbg_port_inst|ci_hex_writer_inst|Selector25~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector25~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(34))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(38))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(34),
	datac => \dbg_port_inst|hex_writer_value\(38),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector25~0_combout\);

-- Location: FF_X27_Y69_N31
\dbg_port_inst|ci_hex_writer_inst|value_buffer[38]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector25~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(38));

-- Location: IOIBUF_X20_Y73_N15
\hex5[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex5(2),
	o => \hex5[2]~input_o\);

-- Location: LCCOMB_X27_Y69_N24
\dbg_port_inst|hex_writer_value[42]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[42]~feeder_combout\ = \hex5[2]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex5[2]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[42]~feeder_combout\);

-- Location: FF_X27_Y69_N25
\dbg_port_inst|hex_writer_value[42]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[42]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(42));

-- Location: LCCOMB_X27_Y69_N18
\dbg_port_inst|ci_hex_writer_inst|Selector21~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector21~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(38))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(42))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(38),
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|hex_writer_value\(42),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector21~0_combout\);

-- Location: FF_X27_Y69_N19
\dbg_port_inst|ci_hex_writer_inst|value_buffer[42]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector21~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(42));

-- Location: IOIBUF_X11_Y73_N15
\hex5[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex5(6),
	o => \hex5[6]~input_o\);

-- Location: LCCOMB_X27_Y69_N28
\dbg_port_inst|hex_writer_value[46]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[46]~feeder_combout\ = \hex5[6]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex5[6]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[46]~feeder_combout\);

-- Location: FF_X27_Y69_N29
\dbg_port_inst|hex_writer_value[46]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[46]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(46));

-- Location: LCCOMB_X27_Y69_N6
\dbg_port_inst|ci_hex_writer_inst|Selector17~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector17~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(42))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(46))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(42),
	datac => \dbg_port_inst|hex_writer_value\(46),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector17~0_combout\);

-- Location: FF_X27_Y69_N7
\dbg_port_inst|ci_hex_writer_inst|value_buffer[46]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector17~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(46));

-- Location: IOIBUF_X23_Y73_N8
\hex6[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex6(2),
	o => \hex6[2]~input_o\);

-- Location: FF_X27_Y69_N1
\dbg_port_inst|hex_writer_value[50]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex6[2]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(50));

-- Location: LCCOMB_X27_Y69_N26
\dbg_port_inst|ci_hex_writer_inst|Selector13~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector13~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(46))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(50))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(46),
	datab => \dbg_port_inst|hex_writer_value\(50),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector13~0_combout\);

-- Location: FF_X27_Y69_N27
\dbg_port_inst|ci_hex_writer_inst|value_buffer[50]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector13~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(50));

-- Location: IOIBUF_X23_Y73_N1
\hex6[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex6(6),
	o => \hex6[6]~input_o\);

-- Location: FF_X27_Y69_N21
\dbg_port_inst|hex_writer_value[54]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex6[6]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(54));

-- Location: LCCOMB_X27_Y69_N22
\dbg_port_inst|ci_hex_writer_inst|Selector9~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector9~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(50))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(54))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(50),
	datab => \dbg_port_inst|hex_writer_value\(54),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector9~0_combout\);

-- Location: FF_X27_Y69_N23
\dbg_port_inst|ci_hex_writer_inst|value_buffer[54]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector9~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(54));

-- Location: IOIBUF_X20_Y73_N22
\hex7[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex7(2),
	o => \hex7[2]~input_o\);

-- Location: LCCOMB_X27_Y69_N8
\dbg_port_inst|hex_writer_value[58]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[58]~feeder_combout\ = \hex7[2]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex7[2]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[58]~feeder_combout\);

-- Location: FF_X27_Y69_N9
\dbg_port_inst|hex_writer_value[58]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[58]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(58));

-- Location: LCCOMB_X27_Y69_N10
\dbg_port_inst|ci_hex_writer_inst|Selector5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector5~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(54))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(58))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(54),
	datab => \dbg_port_inst|hex_writer_value\(58),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector5~0_combout\);

-- Location: FF_X27_Y69_N11
\dbg_port_inst|ci_hex_writer_inst|value_buffer[58]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector5~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(58));

-- Location: IOIBUF_X23_Y73_N22
\hex7[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex7(6),
	o => \hex7[6]~input_o\);

-- Location: LCCOMB_X27_Y69_N12
\dbg_port_inst|hex_writer_value[62]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[62]~feeder_combout\ = \hex7[6]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex7[6]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[62]~feeder_combout\);

-- Location: FF_X27_Y69_N13
\dbg_port_inst|hex_writer_value[62]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[62]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(62));

-- Location: LCCOMB_X27_Y69_N16
\dbg_port_inst|ci_hex_writer_inst|Selector1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector1~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(58))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(62))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(58),
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|hex_writer_value\(62),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector1~0_combout\);

-- Location: FF_X27_Y69_N17
\dbg_port_inst|ci_hex_writer_inst|value_buffer[62]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector1~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(62));

-- Location: LCCOMB_X39_Y47_N6
\dbg_port_inst|ci_hex_writer_inst|digit_to_write~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\ = (\dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(2) & \dbg_port_inst|ci_hex_writer_inst|value_buffer\(62))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(2),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(62),
	combout => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\);

-- Location: IOIBUF_X18_Y73_N15
\hex7[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex7(1),
	o => \hex7[1]~input_o\);

-- Location: LCCOMB_X25_Y69_N16
\dbg_port_inst|hex_writer_value[57]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[57]~feeder_combout\ = \hex7[1]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex7[1]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[57]~feeder_combout\);

-- Location: FF_X25_Y69_N17
\dbg_port_inst|hex_writer_value[57]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[57]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(57));

-- Location: IOIBUF_X20_Y73_N1
\hex6[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex6(1),
	o => \hex6[1]~input_o\);

-- Location: LCCOMB_X25_Y69_N24
\dbg_port_inst|hex_writer_value[49]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[49]~feeder_combout\ = \hex6[1]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex6[1]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[49]~feeder_combout\);

-- Location: FF_X25_Y69_N25
\dbg_port_inst|hex_writer_value[49]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[49]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(49));

-- Location: IOIBUF_X13_Y73_N22
\hex5[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex5(5),
	o => \hex5[5]~input_o\);

-- Location: LCCOMB_X25_Y69_N20
\dbg_port_inst|hex_writer_value[45]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[45]~feeder_combout\ = \hex5[5]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex5[5]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[45]~feeder_combout\);

-- Location: FF_X25_Y69_N21
\dbg_port_inst|hex_writer_value[45]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[45]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(45));

-- Location: IOIBUF_X25_Y73_N15
\hex5[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex5(1),
	o => \hex5[1]~input_o\);

-- Location: LCCOMB_X25_Y69_N0
\dbg_port_inst|hex_writer_value[41]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[41]~feeder_combout\ = \hex5[1]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex5[1]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[41]~feeder_combout\);

-- Location: FF_X25_Y69_N1
\dbg_port_inst|hex_writer_value[41]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[41]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(41));

-- Location: IOIBUF_X16_Y73_N8
\hex4[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex4(5),
	o => \hex4[5]~input_o\);

-- Location: LCCOMB_X25_Y69_N12
\dbg_port_inst|hex_writer_value[37]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[37]~feeder_combout\ = \hex4[5]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex4[5]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[37]~feeder_combout\);

-- Location: FF_X25_Y69_N13
\dbg_port_inst|hex_writer_value[37]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[37]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(37));

-- Location: IOIBUF_X13_Y73_N8
\hex4[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex4(1),
	o => \hex4[1]~input_o\);

-- Location: LCCOMB_X25_Y69_N6
\dbg_port_inst|hex_writer_value[33]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[33]~feeder_combout\ = \hex4[1]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex4[1]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[33]~feeder_combout\);

-- Location: FF_X25_Y69_N7
\dbg_port_inst|hex_writer_value[33]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[33]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(33));

-- Location: IOIBUF_X60_Y73_N1
\ledr[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(1),
	o => \ledr[1]~input_o\);

-- Location: IOIBUF_X60_Y73_N15
\ledg[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(1),
	o => \ledg[1]~input_o\);

-- Location: LCCOMB_X41_Y49_N22
\dbg_port_inst|hex_writer_value~83\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~83_combout\ = (\dbg_port_inst|hex_writer_value[2]~77_combout\ & ((\dbg_port_inst|hex_writer_value[2]~78_combout\ & ((\ledg[1]~input_o\))) # (!\dbg_port_inst|hex_writer_value[2]~78_combout\ & (\ledr[1]~input_o\)))) # 
-- (!\dbg_port_inst|hex_writer_value[2]~77_combout\ & (((!\dbg_port_inst|hex_writer_value[2]~78_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000010101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ledr[1]~input_o\,
	datab => \ledg[1]~input_o\,
	datac => \dbg_port_inst|hex_writer_value[2]~77_combout\,
	datad => \dbg_port_inst|hex_writer_value[2]~78_combout\,
	combout => \dbg_port_inst|hex_writer_value~83_combout\);

-- Location: IOIBUF_X0_Y57_N22
\hex0[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex0(1),
	o => \hex0[1]~input_o\);

-- Location: FF_X41_Y49_N19
\dbg_port_inst|switches[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(1));

-- Location: LCCOMB_X41_Y49_N18
\dbg_port_inst|hex_writer_value~84\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~84_combout\ = (\dbg_port_inst|hex_writer_value~83_combout\ & (((\dbg_port_inst|switches\(1)) # (!\dbg_port_inst|Selector13~0_combout\)))) # (!\dbg_port_inst|hex_writer_value~83_combout\ & (\hex0[1]~input_o\ & 
-- ((\dbg_port_inst|Selector13~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value~83_combout\,
	datab => \hex0[1]~input_o\,
	datac => \dbg_port_inst|switches\(1),
	datad => \dbg_port_inst|Selector13~0_combout\,
	combout => \dbg_port_inst|hex_writer_value~84_combout\);

-- Location: LCCOMB_X42_Y46_N18
\dbg_port_inst|keys[1]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|keys[1]~2_combout\ = !\dbg_port_inst|hex_reader_inst|value\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|keys[1]~2_combout\);

-- Location: FF_X42_Y46_N19
\dbg_port_inst|keys[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|keys[1]~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|keys[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|keys\(1));

-- Location: LCCOMB_X41_Y49_N24
\dbg_port_inst|hex_writer_value~85\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~85_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(1) & ((!\dbg_port_inst|keys\(1)))) # (!\dbg_port_inst|hex_reader_inst|value\(1) & 
-- (\dbg_port_inst|hex_writer_value~84_combout\)))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & (\dbg_port_inst|hex_writer_value~84_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010101011101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value~84_combout\,
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|keys\(1),
	combout => \dbg_port_inst|hex_writer_value~85_combout\);

-- Location: LCCOMB_X40_Y49_N18
\dbg_port_inst|hex_writer_value[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[1]~feeder_combout\ = \dbg_port_inst|hex_writer_value~85_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_writer_value~85_combout\,
	combout => \dbg_port_inst|hex_writer_value[1]~feeder_combout\);

-- Location: LCCOMB_X43_Y46_N28
\dbg_port_inst|nes_buttons_intern[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[1]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|nes_buttons_intern[1]~feeder_combout\);

-- Location: FF_X43_Y46_N29
\dbg_port_inst|nes_buttons_intern[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes_buttons_intern[1]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(1));

-- Location: FF_X40_Y49_N19
\dbg_port_inst|hex_writer_value[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[1]~feeder_combout\,
	asdata => \dbg_port_inst|nes_buttons_intern\(1),
	sload => \dbg_port_inst|hex_reader_inst|value\(3),
	ena => \dbg_port_inst|hex_writer_value[3]~94_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(1));

-- Location: LCCOMB_X40_Y49_N4
\dbg_port_inst|ci_hex_writer_inst|Selector62~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector62~0_combout\ = (\dbg_port_inst|hex_writer_value\(1) & (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & !\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(1),
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector62~0_combout\);

-- Location: FF_X40_Y49_N5
\dbg_port_inst|ci_hex_writer_inst|value_buffer[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector62~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(1));

-- Location: IOIBUF_X0_Y46_N15
\hex0[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex0(5),
	o => \hex0[5]~input_o\);

-- Location: LCCOMB_X43_Y45_N0
\dbg_port_inst|hex_reader_inst|Selector29~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector29~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & \dbg_port_inst|hex_reader_inst|value\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_reader_inst|Selector29~0_combout\);

-- Location: FF_X43_Y45_N1
\dbg_port_inst|hex_reader_inst|value[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector29~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(5));

-- Location: FF_X43_Y46_N9
\dbg_port_inst|switches[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(5),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(5));

-- Location: LCCOMB_X43_Y46_N30
\dbg_port_inst|nes_buttons_intern[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[5]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(5),
	combout => \dbg_port_inst|nes_buttons_intern[5]~feeder_combout\);

-- Location: FF_X43_Y46_N31
\dbg_port_inst|nes_buttons_intern[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes_buttons_intern[5]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(5));

-- Location: IOIBUF_X0_Y46_N22
\ledr[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(5),
	o => \ledr[5]~input_o\);

-- Location: LCCOMB_X43_Y46_N12
\dbg_port_inst|hex_writer_value~64\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~64_combout\ = (\dbg_port_inst|hex_writer_value[6]~54_combout\ & (\dbg_port_inst|nes_buttons_intern\(5) & (\dbg_port_inst|hex_writer_value[6]~53_combout\))) # (!\dbg_port_inst|hex_writer_value[6]~54_combout\ & 
-- (((\ledr[5]~input_o\) # (!\dbg_port_inst|hex_writer_value[6]~53_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011001110000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(5),
	datab => \dbg_port_inst|hex_writer_value[6]~54_combout\,
	datac => \dbg_port_inst|hex_writer_value[6]~53_combout\,
	datad => \ledr[5]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~64_combout\);

-- Location: LCCOMB_X43_Y46_N8
\dbg_port_inst|hex_writer_value~65\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~65_combout\ = (\dbg_port_inst|hex_reader_max_length[0]~3_combout\ & ((\dbg_port_inst|hex_writer_value~64_combout\ & ((\dbg_port_inst|switches\(5)))) # (!\dbg_port_inst|hex_writer_value~64_combout\ & (\hex0[5]~input_o\)))) # 
-- (!\dbg_port_inst|hex_reader_max_length[0]~3_combout\ & (((\dbg_port_inst|hex_writer_value~64_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \hex0[5]~input_o\,
	datab => \dbg_port_inst|hex_reader_max_length[0]~3_combout\,
	datac => \dbg_port_inst|switches\(5),
	datad => \dbg_port_inst|hex_writer_value~64_combout\,
	combout => \dbg_port_inst|hex_writer_value~65_combout\);

-- Location: LCCOMB_X39_Y49_N18
\dbg_port_inst|hex_writer_value[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[5]~feeder_combout\ = \dbg_port_inst|hex_writer_value~65_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_writer_value~65_combout\,
	combout => \dbg_port_inst|hex_writer_value[5]~feeder_combout\);

-- Location: IOIBUF_X0_Y49_N8
\ledg[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(5),
	o => \ledg[5]~input_o\);

-- Location: FF_X39_Y49_N19
\dbg_port_inst|hex_writer_value[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[5]~feeder_combout\,
	asdata => \ledg[5]~input_o\,
	sload => \dbg_port_inst|hex_reader_inst|value\(0),
	ena => \dbg_port_inst|hex_writer_value[4]~58_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(5));

-- Location: LCCOMB_X39_Y49_N2
\dbg_port_inst|ci_hex_writer_inst|Selector58~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector58~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(1))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(1),
	datab => \dbg_port_inst|hex_writer_value\(5),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector58~0_combout\);

-- Location: FF_X39_Y49_N3
\dbg_port_inst|ci_hex_writer_inst|value_buffer[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector58~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(5));

-- Location: IOIBUF_X52_Y73_N8
\ledr[9]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(9),
	o => \ledr[9]~input_o\);

-- Location: LCCOMB_X43_Y45_N8
\dbg_port_inst|hex_reader_inst|Selector25~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector25~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(5) & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(5),
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector25~0_combout\);

-- Location: FF_X43_Y45_N9
\dbg_port_inst|hex_reader_inst|value[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector25~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(9));

-- Location: FF_X43_Y49_N29
\dbg_port_inst|switches[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(9),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(9));

-- Location: IOIBUF_X52_Y73_N1
\hex1[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex1(1),
	o => \hex1[1]~input_o\);

-- Location: LCCOMB_X43_Y49_N28
\dbg_port_inst|hex_writer_value~49\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~49_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (\dbg_port_inst|hex_reader_inst|value\(1) & ((\hex1[1]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(9))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100101010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|switches\(9),
	datad => \hex1[1]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~49_combout\);

-- Location: LCCOMB_X42_Y49_N12
\dbg_port_inst|hex_writer_value~50\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~50_combout\ = (\dbg_port_inst|hex_writer_value~49_combout\) # ((!\dbg_port_inst|hex_reader_inst|value\(1) & \ledr[9]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datab => \ledr[9]~input_o\,
	datad => \dbg_port_inst|hex_writer_value~49_combout\,
	combout => \dbg_port_inst|hex_writer_value~50_combout\);

-- Location: FF_X42_Y49_N13
\dbg_port_inst|hex_writer_value[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~50_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(9));

-- Location: LCCOMB_X39_Y49_N30
\dbg_port_inst|ci_hex_writer_inst|Selector54~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector54~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(5))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(9))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(5),
	datac => \dbg_port_inst|hex_writer_value\(9),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector54~0_combout\);

-- Location: FF_X39_Y49_N31
\dbg_port_inst|ci_hex_writer_inst|value_buffer[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector54~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(9));

-- Location: IOIBUF_X65_Y73_N22
\ledr[13]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(13),
	o => \ledr[13]~input_o\);

-- Location: IOIBUF_X45_Y0_N15
\hex1[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex1(5),
	o => \hex1[5]~input_o\);

-- Location: LCCOMB_X43_Y45_N16
\dbg_port_inst|hex_reader_inst|Selector21~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector21~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & \dbg_port_inst|hex_reader_inst|value\(9))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|value\(9),
	combout => \dbg_port_inst|hex_reader_inst|Selector21~0_combout\);

-- Location: FF_X43_Y45_N17
\dbg_port_inst|hex_reader_inst|value[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector21~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(13));

-- Location: FF_X43_Y45_N3
\dbg_port_inst|switches[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(13),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(13));

-- Location: LCCOMB_X43_Y45_N2
\dbg_port_inst|hex_writer_value~38\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~38_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (\hex1[5]~input_o\ & ((\dbg_port_inst|hex_reader_inst|value\(1))))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(13)) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100000110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \hex1[5]~input_o\,
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|switches\(13),
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_value~38_combout\);

-- Location: LCCOMB_X42_Y49_N6
\dbg_port_inst|hex_writer_value~39\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~39_combout\ = (\dbg_port_inst|hex_writer_value~38_combout\) # ((!\dbg_port_inst|hex_reader_inst|value\(1) & \ledr[13]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \ledr[13]~input_o\,
	datad => \dbg_port_inst|hex_writer_value~38_combout\,
	combout => \dbg_port_inst|hex_writer_value~39_combout\);

-- Location: FF_X42_Y49_N7
\dbg_port_inst|hex_writer_value[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~39_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(13));

-- Location: LCCOMB_X39_Y49_N26
\dbg_port_inst|ci_hex_writer_inst|Selector50~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector50~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(9))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(13))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(9),
	datad => \dbg_port_inst|hex_writer_value\(13),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector50~0_combout\);

-- Location: FF_X39_Y49_N27
\dbg_port_inst|ci_hex_writer_inst|value_buffer[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector50~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(13));

-- Location: LCCOMB_X43_Y45_N12
\dbg_port_inst|hex_reader_inst|Selector17~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector17~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(13) & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(13),
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector17~0_combout\);

-- Location: FF_X43_Y45_N13
\dbg_port_inst|hex_reader_inst|value[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector17~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(17));

-- Location: LCCOMB_X43_Y45_N4
\dbg_port_inst|switches[17]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|switches[17]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(17)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(17),
	combout => \dbg_port_inst|switches[17]~feeder_combout\);

-- Location: FF_X43_Y45_N5
\dbg_port_inst|switches[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|switches[17]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(17));

-- Location: IOIBUF_X47_Y73_N15
\hex2[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex2(1),
	o => \hex2[1]~input_o\);

-- Location: IOIBUF_X58_Y73_N8
\ledr[17]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(17),
	o => \ledr[17]~input_o\);

-- Location: LCCOMB_X43_Y49_N22
\dbg_port_inst|hex_writer_value~32\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~32_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & ((\dbg_port_inst|hex_reader_inst|value\(1) & (\hex2[1]~input_o\)) # (!\dbg_port_inst|hex_reader_inst|value\(1) & ((\ledr[17]~input_o\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010001010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \hex2[1]~input_o\,
	datad => \ledr[17]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~32_combout\);

-- Location: LCCOMB_X42_Y49_N18
\dbg_port_inst|hex_writer_value~92\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~92_combout\ = (\dbg_port_inst|hex_writer_value~32_combout\) # ((\dbg_port_inst|switches\(17) & (!\dbg_port_inst|hex_reader_inst|value\(2) & \dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|switches\(17),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_writer_value~32_combout\,
	combout => \dbg_port_inst|hex_writer_value~92_combout\);

-- Location: FF_X42_Y49_N19
\dbg_port_inst|hex_writer_value[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~92_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(17));

-- Location: LCCOMB_X39_Y49_N12
\dbg_port_inst|ci_hex_writer_inst|Selector46~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector46~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(13))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(17))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(13),
	datad => \dbg_port_inst|hex_writer_value\(17),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector46~0_combout\);

-- Location: FF_X39_Y49_N13
\dbg_port_inst|ci_hex_writer_inst|value_buffer[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector46~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(17));

-- Location: IOIBUF_X31_Y73_N1
\hex2[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex2(5),
	o => \hex2[5]~input_o\);

-- Location: LCCOMB_X32_Y53_N30
\dbg_port_inst|hex_writer_value~26\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~26_combout\ = (\hex2[5]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex2[5]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~26_combout\);

-- Location: FF_X32_Y53_N31
\dbg_port_inst|hex_writer_value[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~26_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(21));

-- Location: LCCOMB_X32_Y53_N6
\dbg_port_inst|ci_hex_writer_inst|Selector42~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector42~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(17))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(21))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(17),
	datac => \dbg_port_inst|hex_writer_value\(21),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector42~0_combout\);

-- Location: FF_X32_Y53_N7
\dbg_port_inst|ci_hex_writer_inst|value_buffer[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector42~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(21));

-- Location: IOIBUF_X31_Y73_N8
\hex3[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex3(1),
	o => \hex3[1]~input_o\);

-- Location: LCCOMB_X32_Y53_N24
\dbg_port_inst|hex_writer_value~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~23_combout\ = (\hex3[1]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111110101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \hex3[1]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~23_combout\);

-- Location: FF_X32_Y53_N25
\dbg_port_inst|hex_writer_value[25]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~23_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(25));

-- Location: LCCOMB_X32_Y53_N28
\dbg_port_inst|ci_hex_writer_inst|Selector38~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector38~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(21))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(25))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(21),
	datab => \dbg_port_inst|hex_writer_value\(25),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector38~0_combout\);

-- Location: FF_X32_Y53_N29
\dbg_port_inst|ci_hex_writer_inst|value_buffer[25]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector38~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(25));

-- Location: IOIBUF_X13_Y73_N15
\hex3[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex3(5),
	o => \hex3[5]~input_o\);

-- Location: LCCOMB_X32_Y53_N22
\dbg_port_inst|hex_writer_value~19\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~19_combout\ = (\hex3[5]~input_o\ & !\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex3[5]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~19_combout\);

-- Location: FF_X32_Y53_N23
\dbg_port_inst|hex_writer_value[29]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~19_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(29));

-- Location: LCCOMB_X32_Y53_N0
\dbg_port_inst|ci_hex_writer_inst|Selector34~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector34~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(25))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(29))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(25),
	datac => \dbg_port_inst|hex_writer_value\(29),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector34~0_combout\);

-- Location: FF_X32_Y53_N1
\dbg_port_inst|ci_hex_writer_inst|value_buffer[29]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector34~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(29));

-- Location: LCCOMB_X25_Y69_N18
\dbg_port_inst|ci_hex_writer_inst|Selector30~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector30~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(29)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(33)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(33),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(29),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector30~0_combout\);

-- Location: FF_X25_Y69_N19
\dbg_port_inst|ci_hex_writer_inst|value_buffer[33]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector30~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(33));

-- Location: LCCOMB_X25_Y69_N14
\dbg_port_inst|ci_hex_writer_inst|Selector26~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector26~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(33)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(37)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(37),
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(33),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector26~0_combout\);

-- Location: FF_X25_Y69_N15
\dbg_port_inst|ci_hex_writer_inst|value_buffer[37]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector26~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(37));

-- Location: LCCOMB_X25_Y69_N26
\dbg_port_inst|ci_hex_writer_inst|Selector22~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector22~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(37)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(41)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(41),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(37),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector22~0_combout\);

-- Location: FF_X25_Y69_N27
\dbg_port_inst|ci_hex_writer_inst|value_buffer[41]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector22~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(41));

-- Location: LCCOMB_X25_Y69_N22
\dbg_port_inst|ci_hex_writer_inst|Selector18~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector18~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(41)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(45)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(45),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(41),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector18~0_combout\);

-- Location: FF_X25_Y69_N23
\dbg_port_inst|ci_hex_writer_inst|value_buffer[45]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector18~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(45));

-- Location: LCCOMB_X25_Y69_N2
\dbg_port_inst|ci_hex_writer_inst|Selector14~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector14~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(45)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(49)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(49),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(45),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector14~0_combout\);

-- Location: FF_X25_Y69_N3
\dbg_port_inst|ci_hex_writer_inst|value_buffer[49]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector14~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(49));

-- Location: IOIBUF_X9_Y73_N8
\hex6[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex6(5),
	o => \hex6[5]~input_o\);

-- Location: FF_X25_Y69_N5
\dbg_port_inst|hex_writer_value[53]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex6[5]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(53));

-- Location: LCCOMB_X25_Y69_N30
\dbg_port_inst|ci_hex_writer_inst|Selector10~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector10~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(49))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(53))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(49),
	datac => \dbg_port_inst|hex_writer_value\(53),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector10~0_combout\);

-- Location: FF_X25_Y69_N31
\dbg_port_inst|ci_hex_writer_inst|value_buffer[53]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector10~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(53));

-- Location: LCCOMB_X25_Y69_N10
\dbg_port_inst|ci_hex_writer_inst|Selector6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector6~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(53)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(57)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(57),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(53),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector6~0_combout\);

-- Location: FF_X25_Y69_N11
\dbg_port_inst|ci_hex_writer_inst|value_buffer[57]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector6~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(57));

-- Location: IOIBUF_X18_Y73_N22
\hex7[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex7(5),
	o => \hex7[5]~input_o\);

-- Location: FF_X25_Y69_N29
\dbg_port_inst|hex_writer_value[61]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex7[5]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(61));

-- Location: LCCOMB_X25_Y69_N8
\dbg_port_inst|ci_hex_writer_inst|Selector2~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector2~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(57))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(61))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(57),
	datab => \dbg_port_inst|hex_writer_value\(61),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector2~0_combout\);

-- Location: FF_X25_Y69_N9
\dbg_port_inst|ci_hex_writer_inst|value_buffer[61]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector2~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(61));

-- Location: LCCOMB_X39_Y47_N28
\dbg_port_inst|ci_hex_writer_inst|digit_to_write~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\ = (\dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(1) & \dbg_port_inst|ci_hex_writer_inst|value_buffer\(61))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(1),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(61),
	combout => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\);

-- Location: IOIBUF_X0_Y53_N8
\hex6[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex6(3),
	o => \hex6[3]~input_o\);

-- Location: LCCOMB_X33_Y53_N20
\dbg_port_inst|hex_writer_value[51]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[51]~feeder_combout\ = \hex6[3]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex6[3]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[51]~feeder_combout\);

-- Location: FF_X33_Y53_N21
\dbg_port_inst|hex_writer_value[51]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[51]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(51));

-- Location: IOIBUF_X11_Y73_N22
\hex5[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex5(3),
	o => \hex5[3]~input_o\);

-- Location: LCCOMB_X33_Y53_N18
\dbg_port_inst|hex_writer_value[43]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[43]~feeder_combout\ = \hex5[3]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex5[3]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[43]~feeder_combout\);

-- Location: FF_X33_Y53_N19
\dbg_port_inst|hex_writer_value[43]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[43]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(43));

-- Location: LCCOMB_X40_Y48_N10
\dbg_port_inst|hex_writer_value[23]~18\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[23]~18_combout\ = (\dbg_port_inst|hex_writer_value[60]~14_combout\ & ((\dbg_port_inst|Equal0~2_combout\) # ((!\dbg_port_inst|Equal0~1_combout\ & \dbg_port_inst|hex_writer_value\(23))))) # 
-- (!\dbg_port_inst|hex_writer_value[60]~14_combout\ & (((\dbg_port_inst|hex_writer_value\(23)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value[60]~14_combout\,
	datab => \dbg_port_inst|Equal0~1_combout\,
	datac => \dbg_port_inst|hex_writer_value\(23),
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value[23]~18_combout\);

-- Location: FF_X40_Y48_N11
\dbg_port_inst|hex_writer_value[23]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[23]~18_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(23));

-- Location: IOIBUF_X0_Y52_N1
\hex3[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex3(3),
	o => \hex3[3]~input_o\);

-- Location: LCCOMB_X32_Y53_N12
\dbg_port_inst|hex_writer_value~22\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~22_combout\ = (\hex3[3]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \hex3[3]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~22_combout\);

-- Location: FF_X32_Y53_N13
\dbg_port_inst|hex_writer_value[27]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~22_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(27));

-- Location: IOIBUF_X7_Y73_N15
\hex2[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex2(3),
	o => \hex2[3]~input_o\);

-- Location: LCCOMB_X32_Y53_N18
\dbg_port_inst|hex_writer_value~31\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~31_combout\ = (\hex2[3]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex2[3]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~31_combout\);

-- Location: FF_X32_Y53_N19
\dbg_port_inst|hex_writer_value[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~31_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(19));

-- Location: IOIBUF_X9_Y73_N1
\ledr[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(3),
	o => \ledr[3]~input_o\);

-- Location: IOIBUF_X72_Y73_N8
\ledg[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(3),
	o => \ledg[3]~input_o\);

-- Location: LCCOMB_X41_Y49_N10
\dbg_port_inst|hex_writer_value~79\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~79_combout\ = (\dbg_port_inst|hex_writer_value[2]~77_combout\ & ((\dbg_port_inst|hex_writer_value[2]~78_combout\ & ((\ledg[3]~input_o\))) # (!\dbg_port_inst|hex_writer_value[2]~78_combout\ & (\ledr[3]~input_o\)))) # 
-- (!\dbg_port_inst|hex_writer_value[2]~77_combout\ & (((!\dbg_port_inst|hex_writer_value[2]~78_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000010101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ledr[3]~input_o\,
	datab => \ledg[3]~input_o\,
	datac => \dbg_port_inst|hex_writer_value[2]~77_combout\,
	datad => \dbg_port_inst|hex_writer_value[2]~78_combout\,
	combout => \dbg_port_inst|hex_writer_value~79_combout\);

-- Location: IOIBUF_X0_Y48_N8
\hex0[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex0(3),
	o => \hex0[3]~input_o\);

-- Location: FF_X41_Y49_N15
\dbg_port_inst|switches[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(3));

-- Location: LCCOMB_X41_Y49_N14
\dbg_port_inst|hex_writer_value~80\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~80_combout\ = (\dbg_port_inst|hex_writer_value~79_combout\ & (((\dbg_port_inst|switches\(3)) # (!\dbg_port_inst|Selector13~0_combout\)))) # (!\dbg_port_inst|hex_writer_value~79_combout\ & (\hex0[3]~input_o\ & 
-- ((\dbg_port_inst|Selector13~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value~79_combout\,
	datab => \hex0[3]~input_o\,
	datac => \dbg_port_inst|switches\(3),
	datad => \dbg_port_inst|Selector13~0_combout\,
	combout => \dbg_port_inst|hex_writer_value~80_combout\);

-- Location: LCCOMB_X42_Y46_N6
\dbg_port_inst|keys[3]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|keys[3]~4_combout\ = !\dbg_port_inst|hex_reader_inst|value\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|value\(3),
	combout => \dbg_port_inst|keys[3]~4_combout\);

-- Location: FF_X42_Y46_N7
\dbg_port_inst|keys[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|keys[3]~4_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|keys[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|keys\(3));

-- Location: LCCOMB_X41_Y49_N20
\dbg_port_inst|hex_writer_value~81\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~81_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(1) & ((!\dbg_port_inst|keys\(3)))) # (!\dbg_port_inst|hex_reader_inst|value\(1) & 
-- (\dbg_port_inst|hex_writer_value~80_combout\)))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & (\dbg_port_inst|hex_writer_value~80_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010101011101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value~80_combout\,
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|keys\(3),
	combout => \dbg_port_inst|hex_writer_value~81_combout\);

-- Location: LCCOMB_X40_Y49_N8
\dbg_port_inst|hex_writer_value[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[3]~feeder_combout\ = \dbg_port_inst|hex_writer_value~81_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_writer_value~81_combout\,
	combout => \dbg_port_inst|hex_writer_value[3]~feeder_combout\);

-- Location: LCCOMB_X46_Y46_N16
\dbg_port_inst|nes_buttons_intern[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[3]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(3),
	combout => \dbg_port_inst|nes_buttons_intern[3]~feeder_combout\);

-- Location: FF_X46_Y46_N17
\dbg_port_inst|nes_buttons_intern[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes_buttons_intern[3]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(3));

-- Location: FF_X40_Y49_N9
\dbg_port_inst|hex_writer_value[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[3]~feeder_combout\,
	asdata => \dbg_port_inst|nes_buttons_intern\(3),
	sload => \dbg_port_inst|hex_reader_inst|value\(3),
	ena => \dbg_port_inst|hex_writer_value[3]~94_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(3));

-- Location: LCCOMB_X40_Y49_N26
\dbg_port_inst|ci_hex_writer_inst|Selector60~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector60~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & (\dbg_port_inst|hex_writer_value\(3) & !\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datab => \dbg_port_inst|hex_writer_value\(3),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector60~0_combout\);

-- Location: FF_X40_Y49_N27
\dbg_port_inst|ci_hex_writer_inst|value_buffer[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector60~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(3));

-- Location: LCCOMB_X40_Y46_N18
\dbg_port_inst|hex_writer_value~62\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~62_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & (((\dbg_port_inst|hex_reader_inst|value\(1)) # (\dbg_port_inst|hex_reader_inst|value\(0))) # (!\dbg_port_inst|hex_reader_inst|value\(2)))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(3) & (\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(1)) # (!\dbg_port_inst|hex_reader_inst|value\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101110100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|hex_writer_value~62_combout\);

-- Location: IOIBUF_X0_Y63_N15
\ledg[7]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(7),
	o => \ledg[7]~input_o\);

-- Location: LCCOMB_X43_Y45_N20
\dbg_port_inst|hex_reader_inst|Selector27~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector27~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(3),
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector27~0_combout\);

-- Location: FF_X43_Y45_N21
\dbg_port_inst|hex_reader_inst|value[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector27~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(7));

-- Location: LCCOMB_X40_Y46_N0
\dbg_port_inst|nes_buttons_intern[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[7]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(7),
	combout => \dbg_port_inst|nes_buttons_intern[7]~feeder_combout\);

-- Location: FF_X40_Y46_N1
\dbg_port_inst|nes_buttons_intern[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes_buttons_intern[7]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(7));

-- Location: LCCOMB_X40_Y46_N6
\dbg_port_inst|hex_writer_value[7]~59\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[7]~59_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & (!\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|nes_buttons_intern\(7))))) # (!\dbg_port_inst|hex_reader_inst|value\(3) & 
-- (\dbg_port_inst|hex_reader_inst|value\(0) & (\ledg[7]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110001001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \ledg[7]~input_o\,
	datad => \dbg_port_inst|nes_buttons_intern\(7),
	combout => \dbg_port_inst|hex_writer_value[7]~59_combout\);

-- Location: FF_X43_Y49_N17
\dbg_port_inst|switches[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(7));

-- Location: IOIBUF_X40_Y0_N15
\ledr[7]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(7),
	o => \ledr[7]~input_o\);

-- Location: LCCOMB_X43_Y49_N16
\dbg_port_inst|hex_writer_value[7]~60\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[7]~60_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (!\dbg_port_inst|hex_reader_inst|value\(1) & ((\ledr[7]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(7))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111001101010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|switches\(7),
	datad => \ledr[7]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[7]~60_combout\);

-- Location: LCCOMB_X40_Y46_N24
\dbg_port_inst|hex_writer_value[7]~61\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[7]~61_combout\ = (\dbg_port_inst|hex_writer_value[7]~59_combout\ & ((\dbg_port_inst|hex_writer_value[4]~57_combout\) # ((\dbg_port_inst|hex_writer_value[16]~30_combout\ & \dbg_port_inst|hex_writer_value[7]~60_combout\)))) # 
-- (!\dbg_port_inst|hex_writer_value[7]~59_combout\ & (\dbg_port_inst|hex_writer_value[16]~30_combout\ & ((\dbg_port_inst|hex_writer_value[7]~60_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110110010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value[7]~59_combout\,
	datab => \dbg_port_inst|hex_writer_value[16]~30_combout\,
	datac => \dbg_port_inst|hex_writer_value[4]~57_combout\,
	datad => \dbg_port_inst|hex_writer_value[7]~60_combout\,
	combout => \dbg_port_inst|hex_writer_value[7]~61_combout\);

-- Location: LCCOMB_X40_Y46_N16
\dbg_port_inst|hex_writer_value[7]~63\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[7]~63_combout\ = (\dbg_port_inst|hex_writer_value[60]~14_combout\ & ((\dbg_port_inst|hex_writer_value~62_combout\ & (\dbg_port_inst|hex_writer_value\(7))) # (!\dbg_port_inst|hex_writer_value~62_combout\ & 
-- ((\dbg_port_inst|hex_writer_value[7]~61_combout\))))) # (!\dbg_port_inst|hex_writer_value[60]~14_combout\ & (((\dbg_port_inst|hex_writer_value\(7)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value[60]~14_combout\,
	datab => \dbg_port_inst|hex_writer_value~62_combout\,
	datac => \dbg_port_inst|hex_writer_value\(7),
	datad => \dbg_port_inst|hex_writer_value[7]~61_combout\,
	combout => \dbg_port_inst|hex_writer_value[7]~63_combout\);

-- Location: FF_X40_Y46_N17
\dbg_port_inst|hex_writer_value[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[7]~63_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(7));

-- Location: LCCOMB_X40_Y49_N6
\dbg_port_inst|ci_hex_writer_inst|Selector56~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector56~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(3))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(7))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(3),
	datab => \dbg_port_inst|hex_writer_value\(7),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector56~0_combout\);

-- Location: FF_X40_Y49_N7
\dbg_port_inst|ci_hex_writer_inst|value_buffer[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector56~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(7));

-- Location: IOIBUF_X49_Y73_N15
\ledr[11]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(11),
	o => \ledr[11]~input_o\);

-- Location: LCCOMB_X43_Y45_N28
\dbg_port_inst|hex_reader_inst|Selector23~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector23~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(7) & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(7),
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector23~0_combout\);

-- Location: FF_X43_Y45_N29
\dbg_port_inst|hex_reader_inst|value[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector23~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(11));

-- Location: FF_X43_Y49_N25
\dbg_port_inst|switches[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(11),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(11));

-- Location: IOIBUF_X54_Y73_N8
\hex1[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex1(3),
	o => \hex1[3]~input_o\);

-- Location: LCCOMB_X43_Y49_N24
\dbg_port_inst|hex_writer_value~47\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~47_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (\dbg_port_inst|hex_reader_inst|value\(1) & ((\hex1[3]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(11))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100101010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|switches\(11),
	datad => \hex1[3]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~47_combout\);

-- Location: LCCOMB_X42_Y49_N10
\dbg_port_inst|hex_writer_value~48\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~48_combout\ = (\dbg_port_inst|hex_writer_value~47_combout\) # ((!\dbg_port_inst|hex_reader_inst|value\(1) & \ledr[11]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \ledr[11]~input_o\,
	datad => \dbg_port_inst|hex_writer_value~47_combout\,
	combout => \dbg_port_inst|hex_writer_value~48_combout\);

-- Location: FF_X42_Y49_N11
\dbg_port_inst|hex_writer_value[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~48_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(11));

-- Location: LCCOMB_X40_Y49_N10
\dbg_port_inst|ci_hex_writer_inst|Selector52~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector52~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(7))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(11))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(7),
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|hex_writer_value\(11),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector52~0_combout\);

-- Location: FF_X40_Y49_N11
\dbg_port_inst|ci_hex_writer_inst|value_buffer[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector52~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(11));

-- Location: LCCOMB_X43_Y49_N8
\dbg_port_inst|hex_reader_inst|Selector19~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector19~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & \dbg_port_inst|hex_reader_inst|value\(11))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|value\(11),
	combout => \dbg_port_inst|hex_reader_inst|Selector19~0_combout\);

-- Location: FF_X43_Y49_N9
\dbg_port_inst|hex_reader_inst|value[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector19~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(15));

-- Location: FF_X41_Y49_N3
\dbg_port_inst|switches[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(15),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(15));

-- Location: IOIBUF_X40_Y73_N1
\ledr[15]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(15),
	o => \ledr[15]~input_o\);

-- Location: LCCOMB_X41_Y49_N2
\dbg_port_inst|hex_writer_value[15]~36\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[15]~36_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (!\dbg_port_inst|hex_reader_inst|value\(1) & ((\ledr[15]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(15))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111001101010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|switches\(15),
	datad => \ledr[15]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[15]~36_combout\);

-- Location: LCCOMB_X40_Y46_N30
\dbg_port_inst|hex_writer_value[15]~37\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[15]~37_combout\ = (\dbg_port_inst|hex_writer_value[60]~14_combout\ & ((\dbg_port_inst|hex_writer_value[16]~30_combout\ & ((\dbg_port_inst|hex_writer_value[15]~36_combout\))) # 
-- (!\dbg_port_inst|hex_writer_value[16]~30_combout\ & (\dbg_port_inst|hex_writer_value\(15))))) # (!\dbg_port_inst|hex_writer_value[60]~14_combout\ & (((\dbg_port_inst|hex_writer_value\(15)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100001110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value[60]~14_combout\,
	datab => \dbg_port_inst|hex_writer_value[16]~30_combout\,
	datac => \dbg_port_inst|hex_writer_value\(15),
	datad => \dbg_port_inst|hex_writer_value[15]~36_combout\,
	combout => \dbg_port_inst|hex_writer_value[15]~37_combout\);

-- Location: FF_X40_Y46_N31
\dbg_port_inst|hex_writer_value[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[15]~37_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(15));

-- Location: LCCOMB_X40_Y49_N22
\dbg_port_inst|ci_hex_writer_inst|Selector48~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector48~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(11))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(15))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(11),
	datac => \dbg_port_inst|hex_writer_value\(15),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector48~0_combout\);

-- Location: FF_X40_Y49_N23
\dbg_port_inst|ci_hex_writer_inst|value_buffer[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector48~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(15));

-- Location: LCCOMB_X33_Y53_N22
\dbg_port_inst|ci_hex_writer_inst|Selector44~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector44~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(15)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(19)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(19),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(15),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector44~0_combout\);

-- Location: FF_X33_Y53_N23
\dbg_port_inst|ci_hex_writer_inst|value_buffer[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector44~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(19));

-- Location: LCCOMB_X33_Y53_N12
\dbg_port_inst|ci_hex_writer_inst|Selector40~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector40~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(19)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(23)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(23),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(19),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector40~0_combout\);

-- Location: FF_X33_Y53_N13
\dbg_port_inst|ci_hex_writer_inst|value_buffer[23]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector40~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(23));

-- Location: LCCOMB_X33_Y53_N2
\dbg_port_inst|ci_hex_writer_inst|Selector36~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector36~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(23)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(27)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111000100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(27),
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(23),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector36~0_combout\);

-- Location: FF_X33_Y53_N3
\dbg_port_inst|ci_hex_writer_inst|value_buffer[27]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector36~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(27));

-- Location: LCCOMB_X33_Y53_N6
\dbg_port_inst|ci_hex_writer_inst|Selector32~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector32~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(27)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(23)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(23),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(27),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector32~0_combout\);

-- Location: FF_X33_Y53_N7
\dbg_port_inst|ci_hex_writer_inst|value_buffer[31]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector32~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(31));

-- Location: IOIBUF_X0_Y53_N1
\hex4[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex4(3),
	o => \hex4[3]~input_o\);

-- Location: FF_X33_Y53_N1
\dbg_port_inst|hex_writer_value[35]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex4[3]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(35));

-- Location: LCCOMB_X33_Y53_N4
\dbg_port_inst|ci_hex_writer_inst|Selector28~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector28~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(31))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(35))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(31),
	datab => \dbg_port_inst|hex_writer_value\(35),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector28~0_combout\);

-- Location: FF_X33_Y53_N5
\dbg_port_inst|ci_hex_writer_inst|value_buffer[35]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector28~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(35));

-- Location: LCCOMB_X33_Y53_N8
\dbg_port_inst|ci_hex_writer_inst|Selector24~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector24~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(35) & \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(35),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector24~0_combout\);

-- Location: FF_X33_Y53_N9
\dbg_port_inst|ci_hex_writer_inst|value_buffer[39]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector24~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(39));

-- Location: LCCOMB_X33_Y53_N14
\dbg_port_inst|ci_hex_writer_inst|Selector20~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector20~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(39)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(43)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(43),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(39),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector20~0_combout\);

-- Location: FF_X33_Y53_N15
\dbg_port_inst|ci_hex_writer_inst|value_buffer[43]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector20~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(43));

-- Location: LCCOMB_X33_Y53_N26
\dbg_port_inst|ci_hex_writer_inst|Selector16~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector16~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(43) & \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(43),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector16~0_combout\);

-- Location: FF_X33_Y53_N27
\dbg_port_inst|ci_hex_writer_inst|value_buffer[47]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector16~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(47));

-- Location: LCCOMB_X33_Y53_N24
\dbg_port_inst|ci_hex_writer_inst|Selector12~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector12~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(47)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(51)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(51),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(47),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector12~0_combout\);

-- Location: FF_X33_Y53_N25
\dbg_port_inst|ci_hex_writer_inst|value_buffer[51]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector12~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(51));

-- Location: LCCOMB_X33_Y53_N28
\dbg_port_inst|ci_hex_writer_inst|Selector8~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector8~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(51) & \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(51),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector8~0_combout\);

-- Location: FF_X33_Y53_N29
\dbg_port_inst|ci_hex_writer_inst|value_buffer[55]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector8~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(55));

-- Location: IOIBUF_X0_Y57_N15
\hex7[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex7(3),
	o => \hex7[3]~input_o\);

-- Location: LCCOMB_X33_Y53_N30
\dbg_port_inst|hex_writer_value[59]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[59]~feeder_combout\ = \hex7[3]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex7[3]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[59]~feeder_combout\);

-- Location: FF_X33_Y53_N31
\dbg_port_inst|hex_writer_value[59]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[59]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(59));

-- Location: LCCOMB_X33_Y53_N10
\dbg_port_inst|ci_hex_writer_inst|Selector4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector4~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(55))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(59))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(55),
	datac => \dbg_port_inst|hex_writer_value\(59),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector4~0_combout\);

-- Location: FF_X33_Y53_N11
\dbg_port_inst|ci_hex_writer_inst|value_buffer[59]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector4~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(59));

-- Location: LCCOMB_X33_Y53_N16
\dbg_port_inst|ci_hex_writer_inst|Selector0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector0~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(59) & \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(59),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector0~0_combout\);

-- Location: FF_X33_Y53_N17
\dbg_port_inst|ci_hex_writer_inst|value_buffer[63]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(63));

-- Location: LCCOMB_X39_Y47_N16
\dbg_port_inst|ci_hex_writer_inst|Selector64~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector64~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\) # ((!\dbg_port_inst|hex_writer_width\(0) & !\dbg_port_inst|hex_writer_width\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101010101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	datac => \dbg_port_inst|hex_writer_width\(0),
	datad => \dbg_port_inst|hex_writer_width\(1),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector64~0_combout\);

-- Location: FF_X39_Y47_N17
\dbg_port_inst|ci_hex_writer_inst|first_digit_mask[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector64~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(3));

-- Location: LCCOMB_X39_Y47_N8
\dbg_port_inst|ci_hex_writer_inst|LessThan0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(63) & (\dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(3) & ((\dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\) # 
-- (\dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(63),
	datad => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(3),
	combout => \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\);

-- Location: IOIBUF_X29_Y73_N1
\hex7[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex7(4),
	o => \hex7[4]~input_o\);

-- Location: LCCOMB_X33_Y69_N20
\dbg_port_inst|hex_writer_value[60]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[60]~feeder_combout\ = \hex7[4]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex7[4]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[60]~feeder_combout\);

-- Location: FF_X33_Y69_N21
\dbg_port_inst|hex_writer_value[60]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[60]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(60));

-- Location: IOIBUF_X25_Y73_N22
\hex6[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex6(4),
	o => \hex6[4]~input_o\);

-- Location: FF_X33_Y69_N13
\dbg_port_inst|hex_writer_value[52]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex6[4]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(52));

-- Location: IOIBUF_X38_Y73_N8
\hex6[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex6(0),
	o => \hex6[0]~input_o\);

-- Location: LCCOMB_X33_Y69_N24
\dbg_port_inst|hex_writer_value[48]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[48]~feeder_combout\ = \hex6[0]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex6[0]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[48]~feeder_combout\);

-- Location: FF_X33_Y69_N25
\dbg_port_inst|hex_writer_value[48]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[48]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(48));

-- Location: IOIBUF_X29_Y73_N8
\hex5[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex5(0),
	o => \hex5[0]~input_o\);

-- Location: FF_X33_Y69_N15
\dbg_port_inst|hex_writer_value[40]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex5[0]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(40));

-- Location: IOIBUF_X35_Y73_N15
\hex4[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex4(4),
	o => \hex4[4]~input_o\);

-- Location: LCCOMB_X36_Y53_N12
\dbg_port_inst|hex_writer_value[36]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[36]~feeder_combout\ = \hex4[4]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex4[4]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[36]~feeder_combout\);

-- Location: FF_X36_Y53_N13
\dbg_port_inst|hex_writer_value[36]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[36]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(36));

-- Location: IOIBUF_X35_Y73_N22
\hex4[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex4(0),
	o => \hex4[0]~input_o\);

-- Location: LCCOMB_X36_Y53_N24
\dbg_port_inst|hex_writer_value[32]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[32]~feeder_combout\ = \hex4[0]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \hex4[0]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[32]~feeder_combout\);

-- Location: FF_X36_Y53_N25
\dbg_port_inst|hex_writer_value[32]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[32]~feeder_combout\,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(32));

-- Location: IOIBUF_X0_Y54_N8
\hex3[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex3(4),
	o => \hex3[4]~input_o\);

-- Location: LCCOMB_X32_Y53_N26
\dbg_port_inst|hex_writer_value~16\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~16_combout\ = (\hex3[4]~input_o\) # (\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex3[4]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~16_combout\);

-- Location: FF_X32_Y53_N27
\dbg_port_inst|hex_writer_value[28]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~16_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(28));

-- Location: IOIBUF_X11_Y73_N1
\hex3[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex3(0),
	o => \hex3[0]~input_o\);

-- Location: LCCOMB_X32_Y53_N10
\dbg_port_inst|hex_writer_value~21\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~21_combout\ = (\hex3[0]~input_o\ & !\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \hex3[0]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~21_combout\);

-- Location: FF_X32_Y53_N11
\dbg_port_inst|hex_writer_value[24]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~21_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(24));

-- Location: IOIBUF_X45_Y0_N22
\hex0[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex0(4),
	o => \hex0[4]~input_o\);

-- Location: LCCOMB_X43_Y45_N30
\dbg_port_inst|hex_reader_inst|Selector30~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector30~0_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	combout => \dbg_port_inst|hex_reader_inst|Selector30~0_combout\);

-- Location: FF_X43_Y45_N31
\dbg_port_inst|hex_reader_inst|value[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector30~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(4));

-- Location: FF_X43_Y45_N25
\dbg_port_inst|switches[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(4));

-- Location: IOIBUF_X72_Y73_N1
\ledr[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(4),
	o => \ledr[4]~input_o\);

-- Location: LCCOMB_X43_Y46_N20
\dbg_port_inst|nes_buttons_intern[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[4]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(4),
	combout => \dbg_port_inst|nes_buttons_intern[4]~feeder_combout\);

-- Location: FF_X43_Y46_N21
\dbg_port_inst|nes_buttons_intern[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes_buttons_intern[4]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(4));

-- Location: LCCOMB_X43_Y46_N26
\dbg_port_inst|hex_writer_value~55\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~55_combout\ = (\dbg_port_inst|hex_writer_value[6]~53_combout\ & ((\dbg_port_inst|hex_writer_value[6]~54_combout\ & ((\dbg_port_inst|nes_buttons_intern\(4)))) # (!\dbg_port_inst|hex_writer_value[6]~54_combout\ & 
-- (\ledr[4]~input_o\)))) # (!\dbg_port_inst|hex_writer_value[6]~53_combout\ & (((\dbg_port_inst|hex_writer_value[6]~54_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ledr[4]~input_o\,
	datab => \dbg_port_inst|nes_buttons_intern\(4),
	datac => \dbg_port_inst|hex_writer_value[6]~53_combout\,
	datad => \dbg_port_inst|hex_writer_value[6]~54_combout\,
	combout => \dbg_port_inst|hex_writer_value~55_combout\);

-- Location: LCCOMB_X43_Y45_N24
\dbg_port_inst|hex_writer_value~56\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~56_combout\ = (\dbg_port_inst|hex_reader_max_length[0]~3_combout\ & ((\dbg_port_inst|hex_writer_value~55_combout\ & (\hex0[4]~input_o\)) # (!\dbg_port_inst|hex_writer_value~55_combout\ & ((\dbg_port_inst|switches\(4)))))) # 
-- (!\dbg_port_inst|hex_reader_max_length[0]~3_combout\ & (((\dbg_port_inst|hex_writer_value~55_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_max_length[0]~3_combout\,
	datab => \hex0[4]~input_o\,
	datac => \dbg_port_inst|switches\(4),
	datad => \dbg_port_inst|hex_writer_value~55_combout\,
	combout => \dbg_port_inst|hex_writer_value~56_combout\);

-- Location: LCCOMB_X39_Y49_N8
\dbg_port_inst|hex_writer_value[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[4]~feeder_combout\ = \dbg_port_inst|hex_writer_value~56_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value~56_combout\,
	combout => \dbg_port_inst|hex_writer_value[4]~feeder_combout\);

-- Location: IOIBUF_X0_Y33_N22
\ledg[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(4),
	o => \ledg[4]~input_o\);

-- Location: FF_X39_Y49_N9
\dbg_port_inst|hex_writer_value[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[4]~feeder_combout\,
	asdata => \ledg[4]~input_o\,
	sload => \dbg_port_inst|hex_reader_inst|value\(0),
	ena => \dbg_port_inst|hex_writer_value[4]~58_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(4));

-- Location: LCCOMB_X45_Y48_N18
\dbg_port_inst|Equal15~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Equal15~0_combout\ = (!\dbg_port_inst|write_address\(3) & (\dbg_port_inst|write_address\(1) & (\dbg_port_inst|write_address\(2) & \dbg_port_inst|write_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|write_address\(3),
	datab => \dbg_port_inst|write_address\(1),
	datac => \dbg_port_inst|write_address\(2),
	datad => \dbg_port_inst|write_address\(0),
	combout => \dbg_port_inst|Equal15~0_combout\);

-- Location: LCCOMB_X43_Y48_N0
\dbg_port_inst|dsc_intern[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|dsc_intern[0]~0_combout\ = (\dbg_port_inst|Equal15~0_combout\ & ((\dbg_port_inst|Selector11~2_combout\ & ((!\dbg_port_inst|hex_reader_inst|value\(0)))) # (!\dbg_port_inst|Selector11~2_combout\ & (\dbg_port_inst|dsc_intern\(0))))) # 
-- (!\dbg_port_inst|Equal15~0_combout\ & (((\dbg_port_inst|dsc_intern\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000011111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|Equal15~0_combout\,
	datab => \dbg_port_inst|Selector11~2_combout\,
	datac => \dbg_port_inst|dsc_intern\(0),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|dsc_intern[0]~0_combout\);

-- Location: FF_X43_Y48_N1
\dbg_port_inst|dsc_intern[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|dsc_intern[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|dsc_intern\(0));

-- Location: IOIBUF_X0_Y34_N8
\ledr[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(0),
	o => \ledr[0]~input_o\);

-- Location: IOIBUF_X40_Y0_N22
\ledg[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(0),
	o => \ledg[0]~input_o\);

-- Location: LCCOMB_X40_Y46_N14
\dbg_port_inst|hex_writer_value~69\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~69_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & (((\dbg_port_inst|hex_reader_inst|value\(1)) # (\ledg[0]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & (\ledr[0]~input_o\ & 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ledr[0]~input_o\,
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \ledg[0]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~69_combout\);

-- Location: IOIBUF_X16_Y73_N15
\hex0[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex0(0),
	o => \hex0[0]~input_o\);

-- Location: LCCOMB_X40_Y46_N8
\dbg_port_inst|hex_writer_value~70\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~70_combout\ = (\dbg_port_inst|hex_reader_inst|value\(1) & ((\dbg_port_inst|hex_writer_value~69_combout\ & (!\dbg_port_inst|dsc_intern\(0))) # (!\dbg_port_inst|hex_writer_value~69_combout\ & ((\hex0[0]~input_o\))))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1) & (((\dbg_port_inst|hex_writer_value~69_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111110001110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|dsc_intern\(0),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|hex_writer_value~69_combout\,
	datad => \hex0[0]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~70_combout\);

-- Location: FF_X41_Y49_N9
\dbg_port_inst|switches[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(0));

-- Location: LCCOMB_X41_Y49_N28
\dbg_port_inst|keys[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|keys[0]~1_combout\ = !\dbg_port_inst|hex_reader_inst|value\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|keys[0]~1_combout\);

-- Location: FF_X41_Y49_N29
\dbg_port_inst|keys[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|keys[0]~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|keys[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|keys\(0));

-- Location: LCCOMB_X41_Y49_N8
\dbg_port_inst|hex_writer_value~71\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~71_combout\ = ((\dbg_port_inst|hex_reader_inst|value\(0) & ((!\dbg_port_inst|keys\(0)))) # (!\dbg_port_inst|hex_reader_inst|value\(0) & (\dbg_port_inst|switches\(0)))) # (!\dbg_port_inst|hex_reader_inst|value\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111010111111101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|switches\(0),
	datad => \dbg_port_inst|keys\(0),
	combout => \dbg_port_inst|hex_writer_value~71_combout\);

-- Location: LCCOMB_X40_Y46_N10
\dbg_port_inst|hex_writer_value~72\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~72_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3) & (\dbg_port_inst|hex_reader_inst|value\(2))) # (!\dbg_port_inst|hex_reader_inst|value\(3) & ((\dbg_port_inst|hex_reader_inst|value\(2) & 
-- (\dbg_port_inst|hex_writer_value~70_combout\)) # (!\dbg_port_inst|hex_reader_inst|value\(2) & ((\dbg_port_inst|hex_writer_value~71_combout\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100111001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_writer_value~70_combout\,
	datad => \dbg_port_inst|hex_writer_value~71_combout\,
	combout => \dbg_port_inst|hex_writer_value~72_combout\);

-- Location: LCCOMB_X52_Y46_N16
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\ = !\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\);

-- Location: LCCOMB_X45_Y48_N24
\dbg_port_inst|Equal17~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|Equal17~0_combout\ = (\dbg_port_inst|write_address\(3) & (\dbg_port_inst|write_address\(1) & (!\dbg_port_inst|write_address\(2) & !\dbg_port_inst|write_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|write_address\(3),
	datab => \dbg_port_inst|write_address\(1),
	datac => \dbg_port_inst|write_address\(2),
	datad => \dbg_port_inst|write_address\(0),
	combout => \dbg_port_inst|Equal17~0_combout\);

-- Location: LCCOMB_X52_Y47_N26
\dbg_port_inst|gfx_data_fifo_input_wr~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_input_wr~feeder_combout\ = \dbg_port_inst|Equal17~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|Equal17~0_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_input_wr~feeder_combout\);

-- Location: FF_X52_Y47_N27
\dbg_port_inst|gfx_data_fifo_input_wr\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_input_wr~feeder_combout\,
	asdata => \~GND~combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_DATA~q\,
	sload => \dbg_port_inst|hex_reader_inst|ALT_INV_done~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_input_wr~q\);

-- Location: LCCOMB_X49_Y46_N14
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\ = (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\ & \dbg_port_inst|gfx_data_fifo_input_wr~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\,
	datad => \dbg_port_inst|gfx_data_fifo_input_wr~q\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\);

-- Location: FF_X52_Y46_N17
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0));

-- Location: LCCOMB_X52_Y46_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~4_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) $ (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~4_combout\);

-- Location: FF_X52_Y46_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~4_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1));

-- Location: LCCOMB_X49_Y46_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2) $ (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & 
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2_combout\);

-- Location: FF_X49_Y46_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2));

-- Location: LCCOMB_X49_Y46_N12
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~3_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3) $ (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~3_combout\);

-- Location: FF_X49_Y46_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3));

-- Location: LCCOMB_X49_Y46_N26
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\);

-- Location: LCCOMB_X49_Y46_N22
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\ $ (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1_combout\);

-- Location: FF_X49_Y46_N23
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4));

-- Location: LCCOMB_X49_Y46_N0
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~5_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5) $ (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\ & 
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~5_combout\);

-- Location: FF_X49_Y46_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~5_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5));

-- Location: LCCOMB_X50_Y46_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\ = !\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\);

-- Location: LCCOMB_X50_Y46_N26
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~0_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1) $ (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~0_combout\);

-- Location: FF_X50_Y46_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1));

-- Location: FF_X50_Y46_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2));

-- Location: LCCOMB_X50_Y46_N12
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2) $ (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1) & 
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\);

-- Location: FF_X50_Y46_N25
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4));

-- Location: LCCOMB_X50_Y46_N24
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4) $ (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\);

-- Location: LCCOMB_X47_Y46_N4
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~0_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\ $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4))))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\ $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001000000001001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~0_combout\);

-- Location: LCCOMB_X50_Y46_N14
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~1_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0) & (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) $ (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1))))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100001000100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~1_combout\);

-- Location: IOIBUF_X115_Y46_N8
\gfx_data_full~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_gfx_data_full,
	o => \gfx_data_full~input_o\);

-- Location: LCCOMB_X49_Y46_N24
\dbg_port_inst|gfx_data_fifo_inst|rd_valid~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|rd_valid~0_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\) # ((\dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ & \gfx_data_full~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\,
	datad => \gfx_data_full~input_o\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~0_combout\);

-- Location: FF_X49_Y46_N25
\dbg_port_inst|gfx_data_fifo_inst|rd_valid\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\);

-- Location: FF_X50_Y46_N31
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(3));

-- Location: LCCOMB_X50_Y46_N30
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(3) $ (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(3),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\);

-- Location: LCCOMB_X49_Y46_N30
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~2_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ & ((\gfx_data_full~input_o\) # (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3) $ 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\)))) # (!\dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3) $ 
-- ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101111001011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3),
	datab => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\,
	datad => \gfx_data_full~input_o\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~2_combout\);

-- Location: LCCOMB_X50_Y46_N16
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~3_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~1_combout\ & (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~2_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~1_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~2_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~3_combout\);

-- Location: LCCOMB_X50_Y46_N4
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~4_combout\ = (\dbg_port_inst|gfx_data_fifo_input_wr~q\) # ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\ & ((!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~3_combout\) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~0_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~3_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\,
	datad => \dbg_port_inst|gfx_data_fifo_input_wr~q\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~4_combout\);

-- Location: FF_X50_Y46_N5
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_next~4_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\);

-- Location: LCCOMB_X49_Y46_N4
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~combout\ = ((\dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ & \gfx_data_full~input_o\)) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110101010101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\,
	datad => \gfx_data_full~input_o\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~combout\);

-- Location: FF_X50_Y46_N7
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0));

-- Location: LCCOMB_X50_Y46_N18
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(3) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(3),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3_combout\);

-- Location: LCCOMB_X50_Y46_N28
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(5) $ (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3_combout\ & 
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~3_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(5),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\);

-- Location: FF_X50_Y46_N29
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(5));

-- Location: LCCOMB_X49_Y46_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Equal1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Equal1~0_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5) $ (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(5) $ 
-- (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\ & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001001101101100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~0_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(5),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Equal1~0_combout\);

-- Location: LCCOMB_X50_Y46_N2
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~2_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0) & (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1))))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) $ (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010010001000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(1),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~2_combout\);

-- Location: LCCOMB_X50_Y46_N20
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~3_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~2_combout\ & (\dbg_port_inst|gfx_data_fifo_input_wr~q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~3_combout\ $ 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(3)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~3_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~2_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(3),
	datad => \dbg_port_inst|gfx_data_fifo_input_wr~q\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~3_combout\);

-- Location: LCCOMB_X49_Y46_N8
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~0_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\ & ((\dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ & ((\gfx_data_full~input_o\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ & (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101000000010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|empty_int~q\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\,
	datad => \gfx_data_full~input_o\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~0_combout\);

-- Location: LCCOMB_X49_Y46_N28
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~1_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2_combout\ $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2))))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1_combout\ & 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2_combout\ $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000001001000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~1_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add1~2_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(4),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~1_combout\);

-- Location: LCCOMB_X49_Y46_N16
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~4_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~0_combout\) # ((!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Equal1~0_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~3_combout\ & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~1_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Equal1~0_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~3_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~0_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~1_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~4_combout\);

-- Location: FF_X49_Y46_N17
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_next~4_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\);

-- Location: IOIBUF_X58_Y73_N22
\gfx_instr_full~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_gfx_instr_full,
	o => \gfx_instr_full~input_o\);

-- Location: LCCOMB_X45_Y48_N30
\dbg_port_inst|gfx_instr_fifo_input_wr~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_input_wr~0_combout\ = (\dbg_port_inst|write_address\(3) & (!\dbg_port_inst|write_address\(1) & (!\dbg_port_inst|write_address\(2) & !\dbg_port_inst|write_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|write_address\(3),
	datab => \dbg_port_inst|write_address\(1),
	datac => \dbg_port_inst|write_address\(2),
	datad => \dbg_port_inst|write_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_input_wr~0_combout\);

-- Location: LCCOMB_X52_Y47_N24
\dbg_port_inst|gfx_instr_fifo_input_wr~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_input_wr~feeder_combout\ = \dbg_port_inst|gfx_instr_fifo_input_wr~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|gfx_instr_fifo_input_wr~0_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_input_wr~feeder_combout\);

-- Location: FF_X52_Y47_N25
\dbg_port_inst|gfx_instr_fifo_input_wr\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_input_wr~feeder_combout\,
	asdata => \~GND~combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|ALT_INV_fsm_state.WRITE_OPERATION_READ_DATA~q\,
	sload => \dbg_port_inst|hex_reader_inst|ALT_INV_done~q\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_input_wr~q\);

-- Location: LCCOMB_X55_Y47_N12
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\ = !\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\);

-- Location: LCCOMB_X52_Y47_N28
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ = (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\ & \dbg_port_inst|gfx_instr_fifo_input_wr~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\,
	datad => \dbg_port_inst|gfx_instr_fifo_input_wr~q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\);

-- Location: FF_X55_Y47_N13
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0));

-- Location: LCCOMB_X52_Y47_N18
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\ = !\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\);

-- Location: LCCOMB_X52_Y47_N20
\dbg_port_inst|gfx_instr_fifo_inst|rd_valid~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~0_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\) # ((\dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\ & \gfx_instr_full~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\,
	datad => \gfx_instr_full~input_o\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~0_combout\);

-- Location: FF_X52_Y47_N21
\dbg_port_inst|gfx_instr_fifo_inst|rd_valid\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\);

-- Location: LCCOMB_X52_Y47_N0
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\ & ((!\dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\) # (!\gfx_instr_full~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \gfx_instr_full~input_o\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\);

-- Location: FF_X52_Y47_N19
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[0]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0));

-- Location: LCCOMB_X52_Y47_N8
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~0_combout\ = \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) $ (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~0_combout\);

-- Location: FF_X52_Y47_N9
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1));

-- Location: LCCOMB_X55_Y47_N16
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~0_combout\ = \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1) $ (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~0_combout\);

-- Location: FF_X55_Y47_N17
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1));

-- Location: LCCOMB_X52_Y47_N22
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~0_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) $ (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) $ (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010010001000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~0_combout\);

-- Location: FF_X52_Y47_N5
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2));

-- Location: LCCOMB_X52_Y47_N4
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~1_combout\ = \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) $ (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & 
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~1_combout\);

-- Location: LCCOMB_X55_Y47_N18
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~1_combout\ = \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) $ (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & 
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~1_combout\);

-- Location: FF_X55_Y47_N19
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2));

-- Location: LCCOMB_X52_Y47_N10
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~1_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~0_combout\ & (!\dbg_port_inst|gfx_instr_fifo_inst|rd~0_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~1_combout\ $ (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~0_combout\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|rd~0_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add0~1_combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~1_combout\);

-- Location: LCCOMB_X52_Y47_N14
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~2_combout\ = (\dbg_port_inst|gfx_instr_fifo_input_wr~q\) # ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\ & !\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~1_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_instr_fifo_input_wr~q\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~1_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~2_combout\);

-- Location: FF_X52_Y47_N15
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_next~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\);

-- Location: LCCOMB_X52_Y47_N16
\dbg_port_inst|gfx_instr_fifo_inst|rd~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|rd~0_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\ & (\gfx_instr_full~input_o\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\ & ((!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \gfx_instr_full~input_o\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|empty_int~q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|rd~0_combout\);

-- Location: LCCOMB_X52_Y47_N12
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~0_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) $ (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) $ (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100001000100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~0_combout\);

-- Location: LCCOMB_X52_Y47_N6
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~1_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~0_combout\ & (\dbg_port_inst|gfx_instr_fifo_input_wr~q\ & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) $ 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~0_combout\,
	datab => \dbg_port_inst|gfx_instr_fifo_input_wr~q\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|Add1~1_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~1_combout\);

-- Location: LCCOMB_X52_Y47_N2
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~2_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~1_combout\) # ((\dbg_port_inst|gfx_instr_fifo_inst|rd~0_combout\ & 
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_instr_fifo_inst|rd~0_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~1_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~2_combout\);

-- Location: FF_X52_Y47_N3
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_next~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\);

-- Location: LCCOMB_X40_Y46_N4
\dbg_port_inst|hex_writer_value~68\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~68_combout\ = (\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(1) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\)) # (!\dbg_port_inst|hex_reader_inst|value\(1) & 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|full_int~q\,
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|full_int~q\,
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|hex_writer_value~68_combout\);

-- Location: LCCOMB_X40_Y46_N2
\dbg_port_inst|nes_buttons_intern[0]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes_buttons_intern[0]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|nes_buttons_intern[0]~feeder_combout\);

-- Location: FF_X40_Y46_N3
\dbg_port_inst|nes_buttons_intern[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes_buttons_intern[0]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes_buttons_intern[4]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes_buttons_intern\(0));

-- Location: LCCOMB_X40_Y46_N28
\dbg_port_inst|hex_writer_value~73\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~73_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(0) & (!\dbg_port_inst|hex_reader_inst|value\(1) & \dbg_port_inst|nes_buttons_intern\(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|nes_buttons_intern\(0),
	combout => \dbg_port_inst|hex_writer_value~73_combout\);

-- Location: LCCOMB_X40_Y46_N22
\dbg_port_inst|hex_writer_value~74\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~74_combout\ = (\dbg_port_inst|hex_writer_value~72_combout\ & (((\dbg_port_inst|hex_writer_value~73_combout\) # (!\dbg_port_inst|hex_reader_inst|value\(3))))) # (!\dbg_port_inst|hex_writer_value~72_combout\ & 
-- (\dbg_port_inst|hex_writer_value~68_combout\ & (\dbg_port_inst|hex_reader_inst|value\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110101001001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value~72_combout\,
	datab => \dbg_port_inst|hex_writer_value~68_combout\,
	datac => \dbg_port_inst|hex_reader_inst|value\(3),
	datad => \dbg_port_inst|hex_writer_value~73_combout\,
	combout => \dbg_port_inst|hex_writer_value~74_combout\);

-- Location: LCCOMB_X42_Y48_N26
\dbg_port_inst|hex_writer_value[0]~76\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[0]~76_combout\ = (\dbg_port_inst|hex_writer_value[60]~14_combout\ & ((\dbg_port_inst|hex_writer_value~75_combout\ & (\dbg_port_inst|hex_writer_value\(0))) # (!\dbg_port_inst|hex_writer_value~75_combout\ & 
-- ((\dbg_port_inst|hex_writer_value~74_combout\))))) # (!\dbg_port_inst|hex_writer_value[60]~14_combout\ & (((\dbg_port_inst|hex_writer_value\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value[60]~14_combout\,
	datab => \dbg_port_inst|hex_writer_value~75_combout\,
	datac => \dbg_port_inst|hex_writer_value\(0),
	datad => \dbg_port_inst|hex_writer_value~74_combout\,
	combout => \dbg_port_inst|hex_writer_value[0]~76_combout\);

-- Location: FF_X42_Y48_N27
\dbg_port_inst|hex_writer_value[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[0]~76_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(0));

-- Location: LCCOMB_X40_Y49_N24
\dbg_port_inst|ci_hex_writer_inst|Selector63~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector63~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\ & ((\dbg_port_inst|hex_writer_value\(0)) # (\dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111000001110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(0),
	datab => \dbg_port_inst|ci_hex_writer_inst|state.SHIFT~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_CHAR~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector63~0_combout\);

-- Location: FF_X40_Y49_N25
\dbg_port_inst|ci_hex_writer_inst|value_buffer[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector63~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(0));

-- Location: LCCOMB_X40_Y49_N12
\dbg_port_inst|ci_hex_writer_inst|Selector59~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector59~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(0)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(4)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(4),
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(0),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector59~0_combout\);

-- Location: FF_X40_Y49_N13
\dbg_port_inst|ci_hex_writer_inst|value_buffer[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector59~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(4));

-- Location: LCCOMB_X43_Y45_N6
\dbg_port_inst|hex_reader_inst|Selector26~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector26~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & \dbg_port_inst|hex_reader_inst|value\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|value\(4),
	combout => \dbg_port_inst|hex_reader_inst|Selector26~0_combout\);

-- Location: FF_X43_Y45_N7
\dbg_port_inst|hex_reader_inst|value[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector26~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(8));

-- Location: FF_X43_Y49_N11
\dbg_port_inst|switches[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(8),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(8));

-- Location: IOIBUF_X0_Y52_N15
\ledg[8]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledg(8),
	o => \ledg[8]~input_o\);

-- Location: IOIBUF_X67_Y73_N8
\hex1[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex1(0),
	o => \hex1[0]~input_o\);

-- Location: IOIBUF_X72_Y73_N15
\ledr[8]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(8),
	o => \ledr[8]~input_o\);

-- Location: LCCOMB_X43_Y49_N0
\dbg_port_inst|hex_writer_value[8]~41\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[8]~41_combout\ = (!\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(1) & (\hex1[0]~input_o\)) # (!\dbg_port_inst|hex_reader_inst|value\(1) & ((\ledr[8]~input_o\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001100100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \hex1[0]~input_o\,
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \ledr[8]~input_o\,
	combout => \dbg_port_inst|hex_writer_value[8]~41_combout\);

-- Location: LCCOMB_X43_Y49_N2
\dbg_port_inst|hex_writer_value[8]~42\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[8]~42_combout\ = (\dbg_port_inst|hex_writer_value[8]~41_combout\) # ((\ledg[8]~input_o\ & (\dbg_port_inst|hex_reader_inst|value\(0) & !\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ledg[8]~input_o\,
	datab => \dbg_port_inst|hex_reader_inst|value\(0),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_writer_value[8]~41_combout\,
	combout => \dbg_port_inst|hex_writer_value[8]~42_combout\);

-- Location: LCCOMB_X43_Y49_N10
\dbg_port_inst|hex_writer_value[8]~43\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[8]~43_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|hex_writer_value[8]~42_combout\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (\dbg_port_inst|Selector13~0_combout\ & 
-- (\dbg_port_inst|switches\(8))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110101001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|Selector13~0_combout\,
	datac => \dbg_port_inst|switches\(8),
	datad => \dbg_port_inst|hex_writer_value[8]~42_combout\,
	combout => \dbg_port_inst|hex_writer_value[8]~43_combout\);

-- Location: LCCOMB_X42_Y48_N24
\dbg_port_inst|hex_writer_value~44\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~44_combout\ = (\dbg_port_inst|hex_reader_inst|value\(3)) # ((\dbg_port_inst|hex_reader_inst|value\(0) & ((\dbg_port_inst|hex_reader_inst|value\(1)) # (!\dbg_port_inst|hex_reader_inst|value\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101110101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(3),
	datab => \dbg_port_inst|hex_reader_inst|value\(2),
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|hex_writer_value~44_combout\);

-- Location: LCCOMB_X40_Y48_N2
\dbg_port_inst|hex_writer_value[8]~45\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[8]~45_combout\ = (\dbg_port_inst|hex_reader_inst|done~q\ & (\res_n~input_o\ & (\dbg_port_inst|fsm_state.READ_OPERATION~q\ & !\dbg_port_inst|hex_writer_value~44_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|done~q\,
	datab => \res_n~input_o\,
	datac => \dbg_port_inst|fsm_state.READ_OPERATION~q\,
	datad => \dbg_port_inst|hex_writer_value~44_combout\,
	combout => \dbg_port_inst|hex_writer_value[8]~45_combout\);

-- Location: LCCOMB_X40_Y48_N0
\dbg_port_inst|hex_writer_value[8]~46\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value[8]~46_combout\ = (\dbg_port_inst|hex_writer_value[8]~45_combout\ & (\dbg_port_inst|hex_writer_value[8]~43_combout\ & (!\dbg_port_inst|hex_reader_inst|value\(3)))) # (!\dbg_port_inst|hex_writer_value[8]~45_combout\ & 
-- (((\dbg_port_inst|hex_writer_value\(8)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value[8]~43_combout\,
	datab => \dbg_port_inst|hex_reader_inst|value\(3),
	datac => \dbg_port_inst|hex_writer_value\(8),
	datad => \dbg_port_inst|hex_writer_value[8]~45_combout\,
	combout => \dbg_port_inst|hex_writer_value[8]~46_combout\);

-- Location: FF_X40_Y48_N1
\dbg_port_inst|hex_writer_value[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value[8]~46_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(8));

-- Location: LCCOMB_X40_Y49_N16
\dbg_port_inst|ci_hex_writer_inst|Selector55~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector55~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(4))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(8))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(4),
	datab => \dbg_port_inst|hex_writer_value\(8),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector55~0_combout\);

-- Location: FF_X40_Y49_N17
\dbg_port_inst|ci_hex_writer_inst|value_buffer[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector55~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(8));

-- Location: IOIBUF_X45_Y73_N1
\ledr[12]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(12),
	o => \ledr[12]~input_o\);

-- Location: LCCOMB_X43_Y45_N22
\dbg_port_inst|hex_reader_inst|Selector22~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector22~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & \dbg_port_inst|hex_reader_inst|value\(8))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|value\(8),
	combout => \dbg_port_inst|hex_reader_inst|Selector22~0_combout\);

-- Location: FF_X43_Y45_N23
\dbg_port_inst|hex_reader_inst|value[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector22~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(12));

-- Location: FF_X43_Y49_N19
\dbg_port_inst|switches[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(12),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(12));

-- Location: IOIBUF_X0_Y50_N15
\hex1[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex1(4),
	o => \hex1[4]~input_o\);

-- Location: LCCOMB_X43_Y49_N18
\dbg_port_inst|hex_writer_value~34\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~34_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (\dbg_port_inst|hex_reader_inst|value\(1) & ((\hex1[4]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(12))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100101010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|switches\(12),
	datad => \hex1[4]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~34_combout\);

-- Location: LCCOMB_X42_Y49_N28
\dbg_port_inst|hex_writer_value~35\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~35_combout\ = (\dbg_port_inst|hex_writer_value~34_combout\) # ((!\dbg_port_inst|hex_reader_inst|value\(1) & \ledr[12]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \ledr[12]~input_o\,
	datad => \dbg_port_inst|hex_writer_value~34_combout\,
	combout => \dbg_port_inst|hex_writer_value~35_combout\);

-- Location: FF_X42_Y49_N29
\dbg_port_inst|hex_writer_value[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~35_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(12));

-- Location: LCCOMB_X39_Y49_N0
\dbg_port_inst|ci_hex_writer_inst|Selector51~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector51~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(8))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(12))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(8),
	datac => \dbg_port_inst|hex_writer_value\(12),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector51~0_combout\);

-- Location: FF_X39_Y49_N1
\dbg_port_inst|ci_hex_writer_inst|value_buffer[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector51~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(12));

-- Location: IOIBUF_X65_Y73_N15
\ledr[16]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_ledr(16),
	o => \ledr[16]~input_o\);

-- Location: LCCOMB_X43_Y49_N26
\dbg_port_inst|hex_reader_inst|Selector18~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_reader_inst|Selector18~0_combout\ = (\dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\ & \dbg_port_inst|hex_reader_inst|value\(12))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|state.PROCESS_CHAR~q\,
	datac => \dbg_port_inst|hex_reader_inst|value\(12),
	combout => \dbg_port_inst|hex_reader_inst|Selector18~0_combout\);

-- Location: FF_X43_Y49_N27
\dbg_port_inst|hex_reader_inst|value[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_reader_inst|Selector18~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|hex_reader_inst|value[1]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_reader_inst|value\(16));

-- Location: FF_X43_Y49_N13
\dbg_port_inst|switches[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(16),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|switches[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|switches\(16));

-- Location: IOIBUF_X67_Y73_N15
\hex2[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex2(0),
	o => \hex2[0]~input_o\);

-- Location: LCCOMB_X43_Y49_N12
\dbg_port_inst|hex_writer_value~28\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~28_combout\ = (\dbg_port_inst|hex_reader_inst|value\(2) & (\dbg_port_inst|hex_reader_inst|value\(1) & ((\hex2[0]~input_o\)))) # (!\dbg_port_inst|hex_reader_inst|value\(2) & (((\dbg_port_inst|switches\(16))) # 
-- (!\dbg_port_inst|hex_reader_inst|value\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100101010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(2),
	datab => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \dbg_port_inst|switches\(16),
	datad => \hex2[0]~input_o\,
	combout => \dbg_port_inst|hex_writer_value~28_combout\);

-- Location: LCCOMB_X42_Y49_N0
\dbg_port_inst|hex_writer_value~29\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~29_combout\ = (\dbg_port_inst|hex_writer_value~28_combout\) # ((!\dbg_port_inst|hex_reader_inst|value\(1) & \ledr[16]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_reader_inst|value\(1),
	datac => \ledr[16]~input_o\,
	datad => \dbg_port_inst|hex_writer_value~28_combout\,
	combout => \dbg_port_inst|hex_writer_value~29_combout\);

-- Location: FF_X42_Y49_N1
\dbg_port_inst|hex_writer_value[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~29_combout\,
	ena => \dbg_port_inst|hex_writer_value[16]~91_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(16));

-- Location: LCCOMB_X36_Y53_N6
\dbg_port_inst|ci_hex_writer_inst|Selector47~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector47~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(12))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(16))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(12),
	datad => \dbg_port_inst|hex_writer_value\(16),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector47~0_combout\);

-- Location: FF_X36_Y53_N7
\dbg_port_inst|ci_hex_writer_inst|value_buffer[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector47~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(16));

-- Location: IOIBUF_X27_Y73_N8
\hex2[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex2(4),
	o => \hex2[4]~input_o\);

-- Location: LCCOMB_X32_Y53_N20
\dbg_port_inst|hex_writer_value~25\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|hex_writer_value~25_combout\ = (\hex2[4]~input_o\ & !\dbg_port_inst|Equal0~2_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \hex2[4]~input_o\,
	datad => \dbg_port_inst|Equal0~2_combout\,
	combout => \dbg_port_inst|hex_writer_value~25_combout\);

-- Location: FF_X32_Y53_N21
\dbg_port_inst|hex_writer_value[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|hex_writer_value~25_combout\,
	ena => \dbg_port_inst|hex_writer_value[28]~90_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(20));

-- Location: LCCOMB_X36_Y53_N4
\dbg_port_inst|ci_hex_writer_inst|Selector43~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector43~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(16))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(20))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(16),
	datac => \dbg_port_inst|hex_writer_value\(20),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector43~0_combout\);

-- Location: FF_X36_Y53_N5
\dbg_port_inst|ci_hex_writer_inst|value_buffer[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector43~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(20));

-- Location: LCCOMB_X36_Y53_N26
\dbg_port_inst|ci_hex_writer_inst|Selector39~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector39~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(20)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(24)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(24),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(20),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector39~0_combout\);

-- Location: FF_X36_Y53_N27
\dbg_port_inst|ci_hex_writer_inst|value_buffer[24]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector39~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(24));

-- Location: LCCOMB_X36_Y53_N22
\dbg_port_inst|ci_hex_writer_inst|Selector35~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector35~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(24)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(28)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(28),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(24),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector35~0_combout\);

-- Location: FF_X36_Y53_N23
\dbg_port_inst|ci_hex_writer_inst|value_buffer[28]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector35~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(28));

-- Location: LCCOMB_X36_Y53_N10
\dbg_port_inst|ci_hex_writer_inst|Selector31~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector31~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(28)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(32)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(32),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(28),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector31~0_combout\);

-- Location: FF_X36_Y53_N11
\dbg_port_inst|ci_hex_writer_inst|value_buffer[32]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector31~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(32));

-- Location: LCCOMB_X36_Y53_N8
\dbg_port_inst|ci_hex_writer_inst|Selector27~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector27~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(32)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(36)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111000100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(36),
	datab => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	datad => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(32),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector27~0_combout\);

-- Location: FF_X36_Y53_N9
\dbg_port_inst|ci_hex_writer_inst|value_buffer[36]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector27~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(36));

-- Location: LCCOMB_X33_Y69_N10
\dbg_port_inst|ci_hex_writer_inst|Selector23~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector23~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(36)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(40)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(40),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(36),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector23~0_combout\);

-- Location: FF_X33_Y69_N11
\dbg_port_inst|ci_hex_writer_inst|value_buffer[40]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector23~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(40));

-- Location: IOIBUF_X33_Y73_N1
\hex5[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex5(4),
	o => \hex5[4]~input_o\);

-- Location: FF_X33_Y69_N29
\dbg_port_inst|hex_writer_value[44]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex5[4]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(44));

-- Location: LCCOMB_X33_Y69_N22
\dbg_port_inst|ci_hex_writer_inst|Selector19~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector19~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(40))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(44))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(40),
	datab => \dbg_port_inst|hex_writer_value\(44),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector19~0_combout\);

-- Location: FF_X33_Y69_N23
\dbg_port_inst|ci_hex_writer_inst|value_buffer[44]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector19~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(44));

-- Location: LCCOMB_X33_Y69_N18
\dbg_port_inst|ci_hex_writer_inst|Selector15~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector15~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(44)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(48)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(48),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(44),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector15~0_combout\);

-- Location: FF_X33_Y69_N19
\dbg_port_inst|ci_hex_writer_inst|value_buffer[48]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector15~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(48));

-- Location: LCCOMB_X33_Y69_N6
\dbg_port_inst|ci_hex_writer_inst|Selector11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector11~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(48)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(52)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|hex_writer_value\(52),
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(48),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector11~0_combout\);

-- Location: FF_X33_Y69_N7
\dbg_port_inst|ci_hex_writer_inst|value_buffer[52]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector11~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(52));

-- Location: IOIBUF_X33_Y73_N8
\hex7[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_hex7(0),
	o => \hex7[0]~input_o\);

-- Location: FF_X33_Y69_N9
\dbg_port_inst|hex_writer_value[56]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \hex7[0]~input_o\,
	sload => VCC,
	ena => \dbg_port_inst|hex_writer_value[60]~89_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|hex_writer_value\(56));

-- Location: LCCOMB_X33_Y69_N26
\dbg_port_inst|ci_hex_writer_inst|Selector7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector7~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(52))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- ((\dbg_port_inst|hex_writer_value\(56))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(52),
	datac => \dbg_port_inst|hex_writer_value\(56),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector7~0_combout\);

-- Location: FF_X33_Y69_N27
\dbg_port_inst|ci_hex_writer_inst|value_buffer[56]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector7~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(56));

-- Location: LCCOMB_X33_Y69_N16
\dbg_port_inst|ci_hex_writer_inst|Selector3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector3~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & ((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(56)))) # (!\dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\ & 
-- (\dbg_port_inst|hex_writer_value\(60)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|hex_writer_value\(60),
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(56),
	datad => \dbg_port_inst|ci_hex_writer_inst|state.IDLE~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector3~0_combout\);

-- Location: FF_X33_Y69_N17
\dbg_port_inst|ci_hex_writer_inst|value_buffer[60]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector3~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|value_buffer[28]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(60));

-- Location: LCCOMB_X40_Y47_N16
\dbg_port_inst|ci_hex_writer_inst|first_digit_mask[0]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|first_digit_mask[0]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask[0]~feeder_combout\);

-- Location: FF_X40_Y47_N17
\dbg_port_inst|ci_hex_writer_inst|first_digit_mask[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask[0]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(0));

-- Location: LCCOMB_X39_Y47_N30
\dbg_port_inst|ci_hex_writer_inst|digit_to_write~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(60) & \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(60),
	datad => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(0),
	combout => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\);

-- Location: LCCOMB_X39_Y47_N24
\dbg_port_inst|ci_hex_writer_inst|Selector88~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector88~4_combout\ = (\dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(1) & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(61) $ (((\dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\ & 
-- !\dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\))))) # (!\dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(1) & (\dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\ & (!\dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010011000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(1),
	datab => \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\,
	datad => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(61),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector88~4_combout\);

-- Location: LCCOMB_X38_Y47_N0
\dbg_port_inst|ci_hex_writer_inst|tx_data[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|tx_data[1]~feeder_combout\ = \dbg_port_inst|ci_hex_writer_inst|Selector88~4_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|ci_hex_writer_inst|Selector88~4_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|tx_data[1]~feeder_combout\);

-- Location: FF_X38_Y47_N1
\dbg_port_inst|ci_hex_writer_inst|tx_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|tx_data[1]~feeder_combout\,
	asdata => VCC,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	ena => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_data\(1));

-- Location: LCCOMB_X38_Y47_N20
\dbg_port_inst|uart_tx_data[1]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_data[1]~1_combout\ = (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & ((\dbg_port_inst|ci_hex_writer_inst|tx_data\(1)))) # (!\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & (\dbg_port_inst|str_writer_inst|tx_data\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|tx_data\(1),
	datab => \dbg_port_inst|ci_hex_writer_inst|tx_data\(1),
	datad => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|uart_tx_data[1]~1_combout\);

-- Location: FF_X39_Y46_N19
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|uart_tx_data[1]~1_combout\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(11));

-- Location: LCCOMB_X35_Y46_N10
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[1]~feeder_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[1]~feeder_combout\);

-- Location: FF_X35_Y46_N11
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[1]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(1));

-- Location: LCCOMB_X35_Y46_N28
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[3]~feeder_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[3]~feeder_combout\);

-- Location: FF_X35_Y46_N29
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[3]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(3));

-- Location: FF_X35_Y46_N7
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(4));

-- Location: LCCOMB_X35_Y46_N16
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[2]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\ = !\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\);

-- Location: FF_X35_Y46_N17
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[2]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(2));

-- Location: LCCOMB_X35_Y46_N6
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~23_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(1) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(2) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(3) $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(4))))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(1) & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(2) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(3) 
-- $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(4)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000001001000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(1),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(3),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(4),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(2),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~23_combout\);

-- Location: LCCOMB_X35_Y46_N26
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\);

-- Location: FF_X35_Y46_N27
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(5));

-- Location: LCCOMB_X35_Y46_N20
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\);

-- Location: FF_X35_Y46_N21
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(7));

-- Location: FF_X35_Y46_N23
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(6));

-- Location: FF_X36_Y46_N19
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|serial_port_inst|transmitter_fifo|Add0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(8));

-- Location: LCCOMB_X35_Y46_N22
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~24_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(5) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(6) & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(7) $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(8))))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(5) & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(6) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(7) 
-- $ (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(8)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(5),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(7),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(6),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(8),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~24_combout\);

-- Location: LCCOMB_X36_Y46_N24
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[0]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[0]~feeder_combout\ = \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[0]~feeder_combout\);

-- Location: FF_X36_Y46_N25
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[0]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(0));

-- Location: LCCOMB_X35_Y46_N0
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~23_combout\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~24_combout\ & 
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~23_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~24_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\);

-- Location: LCCOMB_X39_Y47_N0
\dbg_port_inst|ci_hex_writer_inst|Selector89~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector89~2_combout\ = \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\ $ (((\dbg_port_inst|ci_hex_writer_inst|value_buffer\(60) & \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(60),
	datac => \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\,
	datad => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(0),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector89~2_combout\);

-- Location: FF_X39_Y47_N1
\dbg_port_inst|ci_hex_writer_inst|tx_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector89~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	ena => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_data\(0));

-- Location: LCCOMB_X38_Y48_N10
\dbg_port_inst|str_writer_inst|Mux7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux7~0_combout\ = (\dbg_port_inst|str_writer_inst|idx\(1) & (((\dbg_port_inst|str_writer_str[1][4]~q\ & \dbg_port_inst|str_writer_inst|idx\(0))))) # (!\dbg_port_inst|str_writer_inst|idx\(1) & 
-- ((\dbg_port_inst|str_writer_str[0][1]~q\) # ((!\dbg_port_inst|str_writer_inst|idx\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010001010101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datab => \dbg_port_inst|str_writer_str[0][1]~q\,
	datac => \dbg_port_inst|str_writer_str[1][4]~q\,
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Mux7~0_combout\);

-- Location: LCCOMB_X38_Y48_N30
\dbg_port_inst|str_writer_inst|Mux7~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux7~1_combout\ = (\dbg_port_inst|str_writer_inst|Mux7~0_combout\ & !\dbg_port_inst|str_writer_inst|idx\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|Mux7~0_combout\,
	datac => \dbg_port_inst|str_writer_inst|idx\(2),
	combout => \dbg_port_inst|str_writer_inst|Mux7~1_combout\);

-- Location: FF_X38_Y48_N31
\dbg_port_inst|str_writer_inst|tx_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Mux7~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|tx_data\(0));

-- Location: LCCOMB_X38_Y47_N8
\dbg_port_inst|uart_tx_data[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_data[0]~0_combout\ = (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & (\dbg_port_inst|ci_hex_writer_inst|tx_data\(0))) # (!\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & ((\dbg_port_inst|str_writer_inst|tx_data\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|tx_data\(0),
	datac => \dbg_port_inst|str_writer_inst|tx_data\(0),
	datad => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|uart_tx_data[0]~0_combout\);

-- Location: LCCOMB_X38_Y46_N14
\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~_wirecell\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~_wirecell_combout\ = !\dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|read_address[0]~_wirecell_combout\);

-- Location: LCCOMB_X38_Y48_N4
\dbg_port_inst|str_writer_inst|Mux5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux5~0_combout\ = (!\dbg_port_inst|str_writer_inst|idx\(2) & ((\dbg_port_inst|str_writer_inst|idx\(1) & (\dbg_port_inst|str_writer_str[1][4]~q\ & \dbg_port_inst|str_writer_inst|idx\(0))) # 
-- (!\dbg_port_inst|str_writer_inst|idx\(1) & ((!\dbg_port_inst|str_writer_inst|idx\(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datab => \dbg_port_inst|str_writer_str[1][4]~q\,
	datac => \dbg_port_inst|str_writer_inst|idx\(2),
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Mux5~0_combout\);

-- Location: FF_X38_Y48_N5
\dbg_port_inst|str_writer_inst|tx_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Mux5~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|tx_data\(2));

-- Location: LCCOMB_X39_Y47_N18
\dbg_port_inst|ci_hex_writer_inst|Selector87~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector87~0_combout\ = \dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\ $ (((!\dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\ & (!\dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\ & 
-- \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~0_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\,
	datad => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector87~0_combout\);

-- Location: FF_X39_Y47_N19
\dbg_port_inst|ci_hex_writer_inst|tx_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector87~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sclr => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	ena => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_data\(2));

-- Location: LCCOMB_X38_Y47_N16
\dbg_port_inst|uart_tx_data[2]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_data[2]~2_combout\ = (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & ((\dbg_port_inst|ci_hex_writer_inst|tx_data\(2)))) # (!\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & (\dbg_port_inst|str_writer_inst|tx_data\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	datac => \dbg_port_inst|str_writer_inst|tx_data\(2),
	datad => \dbg_port_inst|ci_hex_writer_inst|tx_data\(2),
	combout => \dbg_port_inst|uart_tx_data[2]~2_combout\);

-- Location: LCCOMB_X39_Y47_N4
\dbg_port_inst|ci_hex_writer_inst|Selector86~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector86~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\ & (!\dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\ & (\dbg_port_inst|ci_hex_writer_inst|value_buffer\(63) & 
-- \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~2_combout\,
	datab => \dbg_port_inst|ci_hex_writer_inst|digit_to_write~1_combout\,
	datac => \dbg_port_inst|ci_hex_writer_inst|value_buffer\(63),
	datad => \dbg_port_inst|ci_hex_writer_inst|first_digit_mask\(3),
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector86~0_combout\);

-- Location: LCCOMB_X38_Y47_N26
\dbg_port_inst|ci_hex_writer_inst|tx_data[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|tx_data[3]~feeder_combout\ = \dbg_port_inst|ci_hex_writer_inst|Selector86~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|ci_hex_writer_inst|Selector86~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|tx_data[3]~feeder_combout\);

-- Location: FF_X38_Y47_N27
\dbg_port_inst|ci_hex_writer_inst|tx_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|tx_data[3]~feeder_combout\,
	asdata => VCC,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	ena => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_data\(3));

-- Location: LCCOMB_X38_Y48_N12
\dbg_port_inst|str_writer_inst|Mux4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux4~0_combout\ = (\dbg_port_inst|str_writer_inst|idx\(0) & (\dbg_port_inst|str_writer_inst|idx\(1) $ (\dbg_port_inst|str_writer_inst|idx\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datac => \dbg_port_inst|str_writer_inst|idx\(2),
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Mux4~0_combout\);

-- Location: LCCOMB_X38_Y48_N16
\dbg_port_inst|str_writer_inst|Mux4~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux4~1_combout\ = (\dbg_port_inst|str_writer_inst|Mux4~0_combout\ & (((\dbg_port_inst|str_writer_str[1][4]~q\)))) # (!\dbg_port_inst|str_writer_inst|Mux4~0_combout\ & (!\dbg_port_inst|str_writer_inst|idx\(2) & 
-- (\dbg_port_inst|str_writer_str[0][1]~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(2),
	datab => \dbg_port_inst|str_writer_str[0][1]~q\,
	datac => \dbg_port_inst|str_writer_str[1][4]~q\,
	datad => \dbg_port_inst|str_writer_inst|Mux4~0_combout\,
	combout => \dbg_port_inst|str_writer_inst|Mux4~1_combout\);

-- Location: FF_X38_Y48_N17
\dbg_port_inst|str_writer_inst|tx_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Mux4~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|tx_data\(3));

-- Location: LCCOMB_X38_Y47_N28
\dbg_port_inst|uart_tx_data[3]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_data[3]~3_combout\ = (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & (\dbg_port_inst|ci_hex_writer_inst|tx_data\(3))) # (!\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & ((\dbg_port_inst|str_writer_inst|tx_data\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|tx_data\(3),
	datac => \dbg_port_inst|str_writer_inst|tx_data\(3),
	datad => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|uart_tx_data[3]~3_combout\);

-- Location: LCCOMB_X38_Y48_N2
\dbg_port_inst|str_writer_inst|Mux3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux3~0_combout\ = (\dbg_port_inst|str_writer_str[1][4]~q\ & ((\dbg_port_inst|str_writer_inst|idx\(1) & (!\dbg_port_inst|str_writer_inst|idx\(2) & !\dbg_port_inst|str_writer_inst|idx\(0))) # 
-- (!\dbg_port_inst|str_writer_inst|idx\(1) & (\dbg_port_inst|str_writer_inst|idx\(2) $ (\dbg_port_inst|str_writer_inst|idx\(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010001001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datab => \dbg_port_inst|str_writer_str[1][4]~q\,
	datac => \dbg_port_inst|str_writer_inst|idx\(2),
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Mux3~0_combout\);

-- Location: FF_X38_Y48_N3
\dbg_port_inst|str_writer_inst|tx_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Mux3~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|tx_data\(4));

-- Location: LCCOMB_X39_Y47_N10
\dbg_port_inst|ci_hex_writer_inst|Selector85~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector85~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\ & !\dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector85~0_combout\);

-- Location: FF_X39_Y47_N11
\dbg_port_inst|ci_hex_writer_inst|tx_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector85~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_data\(4));

-- Location: LCCOMB_X38_Y47_N24
\dbg_port_inst|uart_tx_data[4]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_data[4]~4_combout\ = (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & ((\dbg_port_inst|ci_hex_writer_inst|tx_data\(4)))) # (!\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & (\dbg_port_inst|str_writer_inst|tx_data\(4)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|tx_data\(4),
	datab => \dbg_port_inst|ci_hex_writer_inst|tx_data\(4),
	datad => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|uart_tx_data[4]~4_combout\);

-- Location: LCCOMB_X38_Y47_N12
\dbg_port_inst|ci_hex_writer_inst|tx_data[5]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|tx_data[5]~1_combout\ = !\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	combout => \dbg_port_inst|ci_hex_writer_inst|tx_data[5]~1_combout\);

-- Location: FF_X38_Y47_N13
\dbg_port_inst|ci_hex_writer_inst|tx_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|tx_data[5]~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_data\(5));

-- Location: LCCOMB_X38_Y48_N14
\dbg_port_inst|str_writer_inst|Mux1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|str_writer_inst|Mux1~0_combout\ = (\dbg_port_inst|str_writer_inst|idx\(1) & (\dbg_port_inst|str_writer_str[1][4]~q\ & (!\dbg_port_inst|str_writer_inst|idx\(2)))) # (!\dbg_port_inst|str_writer_inst|idx\(1) & 
-- (((\dbg_port_inst|str_writer_str[1][4]~q\ & !\dbg_port_inst|str_writer_inst|idx\(0))) # (!\dbg_port_inst|str_writer_inst|idx\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110101001101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|str_writer_inst|idx\(1),
	datab => \dbg_port_inst|str_writer_str[1][4]~q\,
	datac => \dbg_port_inst|str_writer_inst|idx\(2),
	datad => \dbg_port_inst|str_writer_inst|idx\(0),
	combout => \dbg_port_inst|str_writer_inst|Mux1~0_combout\);

-- Location: FF_X38_Y48_N15
\dbg_port_inst|str_writer_inst|tx_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|str_writer_inst|Mux1~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|str_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|str_writer_inst|tx_data\(5));

-- Location: LCCOMB_X38_Y47_N22
\dbg_port_inst|uart_tx_data[5]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_data[5]~5_combout\ = (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & (\dbg_port_inst|ci_hex_writer_inst|tx_data\(5))) # (!\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & ((\dbg_port_inst|str_writer_inst|tx_data\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|tx_data\(5),
	datab => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	datad => \dbg_port_inst|str_writer_inst|tx_data\(5),
	combout => \dbg_port_inst|uart_tx_data[5]~5_combout\);

-- Location: LCCOMB_X39_Y47_N22
\dbg_port_inst|ci_hex_writer_inst|Selector83~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|ci_hex_writer_inst|Selector83~0_combout\ = (!\dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\ & \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|ci_hex_writer_inst|state.WRITE_TERM_CHAR~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|LessThan0~0_combout\,
	combout => \dbg_port_inst|ci_hex_writer_inst|Selector83~0_combout\);

-- Location: FF_X39_Y47_N23
\dbg_port_inst|ci_hex_writer_inst|tx_data[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|ci_hex_writer_inst|Selector83~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|ci_hex_writer_inst|tx_wr~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|ci_hex_writer_inst|tx_data\(6));

-- Location: LCCOMB_X38_Y47_N10
\dbg_port_inst|uart_tx_data[6]~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|uart_tx_data[6]~6_combout\ = (\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & (\dbg_port_inst|ci_hex_writer_inst|tx_data\(6))) # (!\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\ & ((\dbg_port_inst|str_writer_inst|tx_data\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|ci_hex_writer_inst|tx_data\(6),
	datab => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	datad => \dbg_port_inst|str_writer_inst|tx_data\(5),
	combout => \dbg_port_inst|uart_tx_data[6]~6_combout\);

-- Location: M9K_X37_Y46_N0
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0\ : cycloneive_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init0 => X"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	init_file => "db/dbg_port_top.ram0_ci_dp_ram_1c1r1w_12035353.hdl.mif",
	init_file_layout => "port_a",
	logical_ram_name => "dbg_port:dbg_port_inst|ci_uart:serial_port_inst|ci_fifo:transmitter_fifo|ci_dp_ram_1c1r1w:memory_inst|altsyncram:ram_rtl_0|altsyncram_70o1:auto_generated|ALTSYNCRAM",
	mixed_port_feed_through_mode => "old",
	operation_mode => "dual_port",
	port_a_address_clear => "none",
	port_a_address_width => 4,
	port_a_byte_enable_clock => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "none",
	port_a_data_width => 36,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 15,
	port_a_logical_ram_depth => 16,
	port_a_logical_ram_width => 8,
	port_a_read_during_write_mode => "new_data_with_nbe_read",
	port_b_address_clear => "none",
	port_b_address_clock => "clock0",
	port_b_address_width => 4,
	port_b_data_out_clear => "none",
	port_b_data_out_clock => "none",
	port_b_data_width => 36,
	port_b_first_address => 0,
	port_b_first_bit_number => 0,
	port_b_last_address => 15,
	port_b_logical_ram_depth => 16,
	port_b_logical_ram_width => 8,
	port_b_read_during_write_mode => "new_data_with_nbe_read",
	port_b_read_enable_clock => "clock0",
	ram_block_type => "M9K")
-- pragma translate_on
PORT MAP (
	portawe => \dbg_port_inst|serial_port_inst|transmitter_fifo|wr_int~combout\,
	portbre => VCC,
	portbaddrstall => \dbg_port_inst|serial_port_inst|transmitter_fifo|ALT_INV_rd_int~combout\,
	clk0 => \clk~inputclkctrl_outclk\,
	portadatain => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
	portaaddr => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
	portbaddr => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portbdataout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);

-- Location: LCCOMB_X35_Y46_N24
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13feeder_combout\);

-- Location: FF_X35_Y46_N25
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\);

-- Location: LCCOMB_X38_Y47_N14
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15feeder_combout\ = \dbg_port_inst|uart_tx_data[1]~1_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|uart_tx_data[1]~1_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15feeder_combout\);

-- Location: LCCOMB_X38_Y46_N12
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~29\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~29_combout\ = (!\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3) & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\ & 
-- ((\dbg_port_inst|ci_hex_writer_inst|tx_wr~q\) # (\dbg_port_inst|str_writer_inst|tx_wr~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(3),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|full_int~q\,
	datac => \dbg_port_inst|ci_hex_writer_inst|tx_wr~q\,
	datad => \dbg_port_inst|str_writer_inst|tx_wr~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~29_combout\);

-- Location: LCCOMB_X38_Y46_N22
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~29_combout\ & (!\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2) & 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0) & !\dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~29_combout\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(2),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(0),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|write_address\(1),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\);

-- Location: FF_X38_Y47_N15
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15_q\);

-- Location: LCCOMB_X39_Y46_N20
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~27\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~27_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\)) 
-- # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100010111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~15_q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~27_combout\);

-- Location: LCCOMB_X39_Y46_N26
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~28\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~28_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(12) & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(11))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~27_combout\))))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(12) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(11)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(12),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(11),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~27_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~28_combout\);

-- Location: FF_X39_Y46_N27
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~28_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(1));

-- Location: LCCOMB_X36_Y46_N14
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\);

-- Location: FF_X36_Y46_N15
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[24]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(24));

-- Location: LCCOMB_X36_Y46_N20
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~41\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~41_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(24) & 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(24),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~41_combout\);

-- Location: FF_X36_Y46_N21
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~41_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(7));

-- Location: LCCOMB_X36_Y45_N0
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[7]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[7]~1_combout\ = (\res_n~input_o\ & ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(7))) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(7)))))) # 
-- (!\res_n~input_o\ & (((\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(7)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(7),
	datab => \res_n~input_o\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(7),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[7]~1_combout\);

-- Location: FF_X36_Y45_N1
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[7]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(7));

-- Location: LCCOMB_X39_Y46_N22
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\);

-- Location: FF_X39_Y46_N23
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(22));

-- Location: FF_X38_Y47_N11
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~20\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|uart_tx_data[6]~6_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~20_q\);

-- Location: LCCOMB_X39_Y46_N28
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~39\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~39_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\)) 
-- # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~20_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~20_q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~39_combout\);

-- Location: LCCOMB_X39_Y46_N10
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[21]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\ = \dbg_port_inst|uart_tx_data[6]~6_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|uart_tx_data[6]~6_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\);

-- Location: FF_X39_Y46_N11
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(21));

-- Location: LCCOMB_X39_Y46_N8
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~40\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~40_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(22) & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & 
-- ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(21)))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~39_combout\)))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(22) & (((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(21)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(22),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~39_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(21),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~40_combout\);

-- Location: FF_X39_Y46_N9
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~40_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(6));

-- Location: LCCOMB_X36_Y45_N6
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector18~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector18~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(7))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(6))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(7),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(6),
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector18~0_combout\);

-- Location: LCCOMB_X36_Y45_N20
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\ = (\res_n~input_o\ & ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\) # 
-- (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datac => \res_n~input_o\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_FIRST~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\);

-- Location: FF_X36_Y45_N7
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector18~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(6));

-- Location: LCCOMB_X36_Y46_N8
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\ = \dbg_port_inst|uart_tx_data[5]~5_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|uart_tx_data[5]~5_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\);

-- Location: FF_X36_Y46_N9
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(19));

-- Location: LCCOMB_X36_Y46_N2
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\);

-- Location: FF_X36_Y46_N3
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(20));

-- Location: LCCOMB_X38_Y47_N30
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19feeder_combout\ = \dbg_port_inst|uart_tx_data[5]~5_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|uart_tx_data[5]~5_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19feeder_combout\);

-- Location: FF_X38_Y47_N31
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19_q\);

-- Location: LCCOMB_X36_Y46_N18
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~37\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~37_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & 
-- ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~19_q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~37_combout\);

-- Location: LCCOMB_X36_Y46_N0
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~38\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~38_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(20) & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(19))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~37_combout\))))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(20) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(19)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111010100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(19),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(20),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~37_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~38_combout\);

-- Location: FF_X36_Y46_N1
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~38_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(5));

-- Location: LCCOMB_X36_Y45_N12
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector19~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector19~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(6))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(6),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(5),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector19~0_combout\);

-- Location: FF_X36_Y45_N13
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector19~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(5));

-- Location: LCCOMB_X36_Y46_N22
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\);

-- Location: FF_X36_Y46_N23
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(18));

-- Location: LCCOMB_X36_Y46_N26
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[17]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\ = \dbg_port_inst|uart_tx_data[4]~4_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|uart_tx_data[4]~4_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\);

-- Location: FF_X36_Y46_N27
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(17));

-- Location: LCCOMB_X38_Y47_N18
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18feeder_combout\ = \dbg_port_inst|uart_tx_data[4]~4_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|uart_tx_data[4]~4_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18feeder_combout\);

-- Location: FF_X38_Y47_N19
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18_q\);

-- Location: LCCOMB_X36_Y46_N12
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~35\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~35_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\)) 
-- # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010110010101100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~18_q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~35_combout\);

-- Location: LCCOMB_X36_Y46_N10
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~36\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~36_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(18) & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(17))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~35_combout\))))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(18) & (((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(17)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(18),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(17),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~35_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~36_combout\);

-- Location: FF_X36_Y46_N11
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~36_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(4));

-- Location: LCCOMB_X36_Y45_N10
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector20~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector20~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(5))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(4))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(5),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(4),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector20~0_combout\);

-- Location: FF_X36_Y45_N11
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector20~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(4));

-- Location: LCCOMB_X36_Y46_N6
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\);

-- Location: FF_X36_Y46_N7
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(16));

-- Location: FF_X36_Y46_N17
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|uart_tx_data[3]~3_combout\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(15));

-- Location: LCCOMB_X38_Y47_N6
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17feeder_combout\ = \dbg_port_inst|uart_tx_data[3]~3_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|uart_tx_data[3]~3_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17feeder_combout\);

-- Location: FF_X38_Y47_N7
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17_q\);

-- Location: LCCOMB_X36_Y46_N28
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~33\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~33_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\)) 
-- # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~17_q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~33_combout\);

-- Location: LCCOMB_X36_Y46_N30
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~34\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~34_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(16) & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(15))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~33_combout\))))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(16) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(15)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(16),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(15),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~33_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~34_combout\);

-- Location: FF_X36_Y46_N31
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~34_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(3));

-- Location: LCCOMB_X36_Y45_N16
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector21~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector21~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(4))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(4),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(3),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector21~0_combout\);

-- Location: FF_X36_Y45_N17
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector21~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(3));

-- Location: FF_X35_Y46_N13
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|uart_tx_data[2]~2_combout\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(13));

-- Location: LCCOMB_X38_Y47_N2
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16feeder_combout\ = \dbg_port_inst|uart_tx_data[2]~2_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|uart_tx_data[2]~2_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16feeder_combout\);

-- Location: FF_X38_Y47_N3
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16_q\);

-- Location: LCCOMB_X36_Y46_N16
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~31\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~31_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\)) 
-- # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~16_q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~31_combout\);

-- Location: LCCOMB_X35_Y46_N14
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\);

-- Location: FF_X35_Y46_N15
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(14));

-- Location: LCCOMB_X36_Y46_N4
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~32\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~32_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(13))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(14) & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~31_combout\))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(14) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(13)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010110010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(13),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~31_combout\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(14),
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~32_combout\);

-- Location: FF_X36_Y46_N5
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~32_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(2));

-- Location: LCCOMB_X36_Y45_N22
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector22~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector22~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(3))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(3),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(2),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector22~0_combout\);

-- Location: FF_X36_Y45_N23
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector22~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(2));

-- Location: LCCOMB_X36_Y45_N18
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector23~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector23~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(2)))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010011100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(1),
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(2),
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector23~0_combout\);

-- Location: FF_X36_Y45_N19
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector23~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(1));

-- Location: FF_X39_Y46_N13
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|uart_tx_data[0]~0_combout\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(9));

-- Location: LCCOMB_X39_Y46_N24
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\);

-- Location: FF_X39_Y46_N25
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass[10]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(10));

-- Location: LCCOMB_X38_Y47_N4
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14feeder_combout\ = \dbg_port_inst|uart_tx_data[0]~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|uart_tx_data[0]~0_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14feeder_combout\);

-- Location: FF_X38_Y47_N5
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14feeder_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14_q\);

-- Location: LCCOMB_X39_Y46_N6
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~22\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~22_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\ & 
-- ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~13_q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~14_q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~22_combout\);

-- Location: LCCOMB_X39_Y46_N16
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~26\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~26_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(10) & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & 
-- (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(9))) # (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~22_combout\))))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(10) & (\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(9)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111010100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(9),
	datab => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram_rtl_0_bypass\(10),
	datac => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~25_combout\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~22_combout\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~26_combout\);

-- Location: FF_X39_Y46_N17
\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|ram~26_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_fifo|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(0));

-- Location: LCCOMB_X36_Y45_N24
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector24~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector24~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & (\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(1))) # 
-- (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\ & ((\dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(1),
	datad => \dbg_port_inst|serial_port_inst|transmitter_fifo|memory_inst|rd1_data\(0),
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector24~0_combout\);

-- Location: FF_X36_Y45_N25
\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector24~0_combout\,
	ena => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data[5]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(0));

-- Location: LCCOMB_X38_Y45_N6
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~0_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(0) & ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\) # 
-- ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\) # (\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_NEXT~q\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP_NEXT~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmit_data\(0),
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~0_combout\);

-- Location: LCCOMB_X38_Y45_N26
\dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~1_combout\ = (\dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~0_combout\) # ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\) # 
-- ((\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\) # (!\dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~0_combout\,
	datab => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.NEW_DATA~q\,
	datac => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.TRANSMIT_STOP~q\,
	datad => \dbg_port_inst|serial_port_inst|transmitter_inst|transmitter_state.IDLE~q\,
	combout => \dbg_port_inst|serial_port_inst|transmitter_inst|Selector17~1_combout\);

-- Location: LCCOMB_X55_Y47_N2
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\ = (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & !\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\);

-- Location: FF_X53_Y45_N3
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~44\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~44_q\);

-- Location: LCCOMB_X55_Y47_N24
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & !\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\);

-- Location: FF_X53_Y45_N25
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~52\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~52_q\);

-- Location: LCCOMB_X53_Y45_N2
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~52_q\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~44_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~44_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~52_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\);

-- Location: LCCOMB_X55_Y47_N4
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\);

-- Location: FF_X53_Y46_N27
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~68\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~68_q\);

-- Location: LCCOMB_X55_Y47_N30
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\ = (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\);

-- Location: FF_X53_Y46_N1
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~60\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~60_q\);

-- Location: LCCOMB_X53_Y46_N26
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~77\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~68_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~60_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~68_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~60_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\);

-- Location: LCCOMB_X53_Y47_N18
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36feeder_combout\);

-- Location: LCCOMB_X55_Y47_N28
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\);

-- Location: FF_X53_Y47_N19
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\);

-- Location: LCCOMB_X55_Y47_N6
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\ = (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\);

-- Location: FF_X53_Y47_N1
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~28\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\);

-- Location: LCCOMB_X55_Y47_N26
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\ = (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & !\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\);

-- Location: FF_X54_Y47_N19
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~12\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~12_q\);

-- Location: LCCOMB_X55_Y47_N0
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\ & !\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(0),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(2),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|write_address\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\);

-- Location: FF_X54_Y47_N17
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~20\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~20_q\);

-- Location: LCCOMB_X54_Y47_N18
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~20_q\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~12_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~12_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~20_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78_combout\);

-- Location: LCCOMB_X53_Y47_N0
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~79\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~79_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~78_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~79_combout\);

-- Location: LCCOMB_X54_Y46_N8
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~80\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~80_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~79_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~79_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~80_combout\);

-- Location: FF_X54_Y46_N9
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~80_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(0));

-- Location: FF_X53_Y45_N7
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~45\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~45_q\);

-- Location: LCCOMB_X53_Y45_N12
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53feeder_combout\);

-- Location: FF_X53_Y45_N13
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53_q\);

-- Location: LCCOMB_X53_Y45_N6
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53_q\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~45_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~45_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~53_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81_combout\);

-- Location: FF_X53_Y46_N13
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~69\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~69_q\);

-- Location: FF_X54_Y46_N25
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~61\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~61_q\);

-- Location: LCCOMB_X53_Y46_N12
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~82\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~82_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~69_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~61_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~81_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~69_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~61_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~82_combout\);

-- Location: LCCOMB_X53_Y47_N14
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37feeder_combout\);

-- Location: FF_X53_Y47_N15
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\);

-- Location: FF_X54_Y47_N13
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~21\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~21_q\);

-- Location: FF_X54_Y47_N7
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~13\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~13_q\);

-- Location: LCCOMB_X53_Y47_N12
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29feeder_combout\);

-- Location: FF_X53_Y47_N13
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\);

-- Location: LCCOMB_X54_Y47_N6
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)) # 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~13_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~13_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83_combout\);

-- Location: LCCOMB_X54_Y47_N12
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~84\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~84_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~21_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~21_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~83_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~84_combout\);

-- Location: LCCOMB_X54_Y46_N26
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~85\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~85_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~82_combout\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~84_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~82_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~84_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~85_combout\);

-- Location: FF_X54_Y46_N27
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~85_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(1));

-- Location: LCCOMB_X53_Y45_N8
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54feeder_combout\);

-- Location: FF_X53_Y45_N9
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54_q\);

-- Location: FF_X53_Y45_N19
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~46\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~46_q\);

-- Location: LCCOMB_X53_Y45_N18
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54_q\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~46_q\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~54_q\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~46_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86_combout\);

-- Location: FF_X53_Y46_N9
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~70\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~70_q\);

-- Location: FF_X53_Y46_N7
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~62\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~62_q\);

-- Location: LCCOMB_X53_Y46_N8
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~87\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~87_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~70_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~62_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~86_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~70_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~62_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~87_combout\);

-- Location: LCCOMB_X53_Y47_N2
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38feeder_combout\);

-- Location: FF_X53_Y47_N3
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\);

-- Location: FF_X54_Y47_N9
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~22\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~22_q\);

-- Location: FF_X54_Y47_N11
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~14\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~14_q\);

-- Location: LCCOMB_X53_Y47_N8
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30feeder_combout\);

-- Location: FF_X53_Y47_N9
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\);

-- Location: LCCOMB_X54_Y47_N10
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)) # 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~14_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~14_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88_combout\);

-- Location: LCCOMB_X54_Y47_N8
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~89\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~89_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~22_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~22_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~88_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~89_combout\);

-- Location: LCCOMB_X54_Y46_N20
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~90\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~90_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~87_combout\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~89_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~87_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~89_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~90_combout\);

-- Location: FF_X54_Y46_N21
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~90_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(2));

-- Location: FF_X53_Y45_N5
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~55\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~55_q\);

-- Location: FF_X53_Y45_N23
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~47\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~47_q\);

-- Location: LCCOMB_X53_Y45_N22
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~55_q\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~47_q\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~55_q\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~47_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91_combout\);

-- Location: FF_X53_Y46_N5
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~71\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~71_q\);

-- Location: FF_X53_Y46_N11
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~63\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~63_q\);

-- Location: LCCOMB_X53_Y46_N4
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~92\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~92_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~71_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~63_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~91_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~71_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~63_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~92_combout\);

-- Location: FF_X53_Y47_N7
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~39\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\);

-- Location: FF_X54_Y47_N15
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~15\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~15_q\);

-- Location: FF_X53_Y47_N5
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~31\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\);

-- Location: LCCOMB_X54_Y47_N14
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~93\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~93_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)) # 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~15_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~15_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~93_combout\);

-- Location: FF_X54_Y47_N5
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~23\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\);

-- Location: LCCOMB_X54_Y47_N4
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~94\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~94_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~93_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\) # 
-- ((!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~93_combout\ & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & 
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~93_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~94_combout\);

-- Location: LCCOMB_X54_Y46_N14
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~95\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~95_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~92_combout\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~94_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~92_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~94_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~95_combout\);

-- Location: FF_X54_Y46_N15
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~95_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(3));

-- Location: FF_X53_Y47_N27
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~40\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~40_q\);

-- Location: FF_X54_Y47_N27
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~16\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~16_q\);

-- Location: FF_X53_Y47_N25
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~32\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\);

-- Location: LCCOMB_X54_Y47_N26
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~98\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~98_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)) # 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~16_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~16_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~98_combout\);

-- Location: FF_X54_Y47_N1
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~24\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\);

-- Location: LCCOMB_X54_Y47_N0
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~99\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~99_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~98_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~40_q\) # 
-- ((!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~98_combout\ & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\ & 
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~40_q\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~98_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~99_combout\);

-- Location: FF_X53_Y46_N15
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~64\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~64_q\);

-- Location: FF_X53_Y46_N25
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~72\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~72_q\);

-- Location: FF_X53_Y45_N27
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~48\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~48_q\);

-- Location: FF_X53_Y45_N1
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~56\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~56_q\);

-- Location: LCCOMB_X53_Y45_N26
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~56_q\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~48_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~48_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~56_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96_combout\);

-- Location: LCCOMB_X53_Y46_N24
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~97\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~97_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96_combout\ & 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~72_q\))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96_combout\ & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~64_q\)))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~64_q\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~72_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~96_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~97_combout\);

-- Location: LCCOMB_X54_Y46_N0
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~100\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~100_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~97_combout\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~99_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101011001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~99_combout\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~97_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~100_combout\);

-- Location: FF_X54_Y46_N1
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~100_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(4));

-- Location: FF_X53_Y45_N31
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~49\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(5),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~49_q\);

-- Location: FF_X53_Y45_N21
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~57\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(5),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~57_q\);

-- Location: LCCOMB_X53_Y45_N30
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~57_q\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~49_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~49_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~57_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101_combout\);

-- Location: FF_X53_Y46_N29
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~73\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(5),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~73_q\);

-- Location: LCCOMB_X53_Y46_N2
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(5),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65feeder_combout\);

-- Location: FF_X53_Y46_N3
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65_q\);

-- Location: LCCOMB_X53_Y46_N28
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~102\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~102_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~73_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~101_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~73_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~65_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~102_combout\);

-- Location: FF_X54_Y47_N23
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~17\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(5),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~17_q\);

-- Location: LCCOMB_X53_Y47_N20
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(5),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33feeder_combout\);

-- Location: FF_X53_Y47_N21
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\);

-- Location: LCCOMB_X54_Y47_N22
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~103\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~103_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)) # 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~17_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~17_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~103_combout\);

-- Location: FF_X54_Y47_N29
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~25\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(5),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\);

-- Location: LCCOMB_X53_Y47_N30
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(5),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41feeder_combout\);

-- Location: FF_X53_Y47_N31
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41_q\);

-- Location: LCCOMB_X54_Y47_N28
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~104\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~104_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~103_combout\ & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41_q\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~103_combout\ & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110101001100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~103_combout\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~41_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~104_combout\);

-- Location: LCCOMB_X54_Y46_N2
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~105\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~105_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~102_combout\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~104_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~102_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~104_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~105_combout\);

-- Location: FF_X54_Y46_N3
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~105_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(5));

-- Location: FF_X53_Y45_N11
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~50\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~50_q\);

-- Location: FF_X53_Y45_N17
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~58\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~58_q\);

-- Location: LCCOMB_X53_Y45_N10
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~58_q\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~50_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~50_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~58_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106_combout\);

-- Location: FF_X53_Y46_N17
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~74\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~74_q\);

-- Location: FF_X53_Y46_N31
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~66\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~66_q\);

-- Location: LCCOMB_X53_Y46_N16
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~107\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~107_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~74_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~66_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~106_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~74_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~66_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~107_combout\);

-- Location: LCCOMB_X53_Y47_N10
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(6),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42feeder_combout\);

-- Location: FF_X53_Y47_N11
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42_q\);

-- Location: FF_X54_Y47_N25
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~26\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\);

-- Location: FF_X54_Y47_N3
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~18\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~18_q\);

-- Location: LCCOMB_X53_Y47_N16
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(6),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34feeder_combout\);

-- Location: FF_X53_Y47_N17
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\);

-- Location: LCCOMB_X54_Y47_N2
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)) # 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~18_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~18_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108_combout\);

-- Location: LCCOMB_X54_Y47_N24
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~109\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~109_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~42_q\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~108_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~109_combout\);

-- Location: LCCOMB_X54_Y46_N4
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~110\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~110_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~107_combout\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~109_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~107_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~109_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~110_combout\);

-- Location: FF_X54_Y46_N5
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~110_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(6));

-- Location: FF_X53_Y45_N15
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~51\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~118_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~51_q\);

-- Location: FF_X53_Y45_N29
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~59\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~117_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~59_q\);

-- Location: LCCOMB_X53_Y45_N14
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~59_q\))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~51_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~51_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~59_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111_combout\);

-- Location: FF_X53_Y46_N21
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~75\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~119_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~75_q\);

-- Location: FF_X53_Y46_N19
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~67\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~116_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~67_q\);

-- Location: LCCOMB_X53_Y46_N20
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~112\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~112_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111_combout\ & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~75_q\)) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111_combout\ & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~67_q\))))) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~111_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~75_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~67_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~112_combout\);

-- Location: FF_X54_Y47_N31
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~19\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~122_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~19_q\);

-- Location: LCCOMB_X53_Y47_N28
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(7),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35feeder_combout\);

-- Location: FF_X53_Y47_N29
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~120_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\);

-- Location: LCCOMB_X54_Y47_N30
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~113\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~113_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)) # 
-- ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1) & (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~19_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(1),
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~19_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~113_combout\);

-- Location: FF_X54_Y47_N21
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~27\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	sload => VCC,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~121_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\);

-- Location: LCCOMB_X53_Y47_N22
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(7),
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43feeder_combout\);

-- Location: FF_X53_Y47_N23
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43feeder_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~123_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43_q\);

-- Location: LCCOMB_X54_Y47_N20
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~114\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~114_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~113_combout\ & (((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43_q\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0)))) # (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~113_combout\ & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0) & 
-- (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110101001100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~113_combout\,
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(0),
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~43_q\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~114_combout\);

-- Location: LCCOMB_X54_Y46_N22
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~115\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~115_combout\ = (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & (\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~112_combout\)) # 
-- (!\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2) & ((\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~114_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~112_combout\,
	datac => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|read_address\(2),
	datad => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~114_combout\,
	combout => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~115_combout\);

-- Location: FF_X54_Y46_N23
\dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|ram~115_combout\,
	ena => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_instr_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(7));

-- Location: LCCOMB_X52_Y47_N30
\dbg_port_inst|gfx_instr_rd_ack\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_instr_rd_ack~combout\ = (!\gfx_instr_full~input_o\ & \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \gfx_instr_full~input_o\,
	datad => \dbg_port_inst|gfx_instr_fifo_inst|rd_valid~q\,
	combout => \dbg_port_inst|gfx_instr_rd_ack~combout\);

-- Location: LCCOMB_X45_Y46_N18
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[13]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\);

-- Location: FF_X45_Y46_N19
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[13]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(13));

-- Location: LCCOMB_X47_Y46_N22
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\);

-- Location: FF_X47_Y46_N23
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[5]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(5));

-- Location: LCCOMB_X47_Y46_N24
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\);

-- Location: FF_X47_Y46_N25
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[7]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(7));

-- Location: FF_X47_Y46_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(6));

-- Location: LCCOMB_X47_Y46_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[8]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~2_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\);

-- Location: FF_X47_Y46_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[8]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(8));

-- Location: LCCOMB_X47_Y46_N12
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~42\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~42_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(5) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(6) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(7) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(8))))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(5) & 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(6) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(7) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(8)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(5),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(7),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(6),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(8),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~42_combout\);

-- Location: LCCOMB_X47_Y46_N30
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[9]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\ = \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\);

-- Location: FF_X47_Y46_N31
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[9]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(9));

-- Location: FF_X47_Y46_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(11));

-- Location: FF_X47_Y46_N29
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~4_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(10));

-- Location: FF_X47_Y46_N27
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~5_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(12));

-- Location: LCCOMB_X47_Y46_N28
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~43\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~43_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(9) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(10) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(11) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(12))))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(9) 
-- & (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(10) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(11) $ 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(12)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(9),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(11),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(10),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(12),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~43_combout\);

-- Location: FF_X49_Y46_N15
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(0));

-- Location: FF_X47_Y46_N21
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(3));

-- Location: FF_X49_Y46_N5
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(1));

-- Location: FF_X50_Y46_N9
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|Add0~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(4));

-- Location: LCCOMB_X50_Y46_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[2]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[2]~0_combout\ = !\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[2]~0_combout\);

-- Location: FF_X50_Y46_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[2]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(2));

-- Location: LCCOMB_X50_Y46_N8
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~41\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~41_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(3) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(4) & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(1) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(2))))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(3) & 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(4) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(1) $ (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(3),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(1),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(4),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(2),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~41_combout\);

-- Location: LCCOMB_X47_Y46_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~42_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~43_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(0) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~41_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~42_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~43_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(0),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~41_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\);

-- Location: LCCOMB_X48_Y46_N30
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23feeder_combout\);

-- Location: FF_X48_Y46_N31
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\);

-- Location: LCCOMB_X49_Y46_N2
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~76\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\ = (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2) & (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1) & 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0) & !\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(2),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(1),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(0),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(3),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\);

-- Location: LCCOMB_X49_Y46_N20
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\ = (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\ & 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4) & \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(5),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|write_address\(4),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~76_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\);

-- Location: FF_X48_Y46_N5
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~24\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(0),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\);

-- Location: LCCOMB_X48_Y46_N14
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~_wirecell\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~_wirecell_combout\ = !\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|rd_int~_wirecell_combout\);

-- Location: LCCOMB_X50_Y46_N22
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~_wirecell\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~_wirecell_combout\ = !\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address\(0),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|read_address[0]~_wirecell_combout\);

-- Location: M9K_X51_Y46_N0
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0\ : cycloneive_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init1 => X"0000000000000000000000000000000000000000000000000000000000000000",
	mem_init0 => X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	init_file => "db/dbg_port_top.ram0_ci_dp_ram_1c1r1w_d43d7026.hdl.mif",
	init_file_layout => "port_a",
	logical_ram_name => "dbg_port:dbg_port_inst|ci_fwft_fifo:gfx_data_fifo_inst|ci_fifo:ci_fifo_inst|ci_dp_ram_1c1r1w:memory_inst|altsyncram:ram_rtl_0|altsyncram_n6o1:auto_generated|ALTSYNCRAM",
	mixed_port_feed_through_mode => "old",
	operation_mode => "dual_port",
	port_a_address_clear => "none",
	port_a_address_width => 6,
	port_a_byte_enable_clock => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "none",
	port_a_data_width => 36,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 63,
	port_a_logical_ram_depth => 64,
	port_a_logical_ram_width => 16,
	port_a_read_during_write_mode => "new_data_with_nbe_read",
	port_b_address_clear => "none",
	port_b_address_clock => "clock0",
	port_b_address_width => 6,
	port_b_data_out_clear => "none",
	port_b_data_out_clock => "none",
	port_b_data_width => 36,
	port_b_first_address => 0,
	port_b_first_bit_number => 0,
	port_b_last_address => 63,
	port_b_logical_ram_depth => 64,
	port_b_logical_ram_width => 16,
	port_b_read_during_write_mode => "new_data_with_nbe_read",
	port_b_read_enable_clock => "clock0",
	ram_block_type => "M9K")
-- pragma translate_on
PORT MAP (
	portawe => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|wr_int~combout\,
	portbre => VCC,
	portbaddrstall => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~_wirecell_combout\,
	clk0 => \clk~inputclkctrl_outclk\,
	portadatain => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
	portaaddr => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
	portbaddr => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portbdataout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);

-- Location: LCCOMB_X48_Y46_N4
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~40\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~40_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & 
-- ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~24_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a0~portbdataout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~40_combout\);

-- Location: LCCOMB_X45_Y46_N28
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[14]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\);

-- Location: FF_X45_Y46_N29
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[14]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(14));

-- Location: LCCOMB_X48_Y46_N16
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~45\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~45_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(13))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(14) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~40_combout\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(14) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(13)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(13),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~40_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(14),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~45_combout\);

-- Location: FF_X48_Y46_N17
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~45_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(0));

-- Location: LCCOMB_X45_Y46_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[15]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[15]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|value\(1),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[15]~feeder_combout\);

-- Location: FF_X45_Y46_N7
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[15]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(15));

-- Location: LCCOMB_X45_Y46_N0
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[16]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\);

-- Location: FF_X45_Y46_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[16]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(16));

-- Location: FF_X48_Y46_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~25\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(1),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\);

-- Location: LCCOMB_X48_Y46_N0
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~46\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~46_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~25_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a1\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~46_combout\);

-- Location: LCCOMB_X48_Y46_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~47\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~47_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(15))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(16) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~46_combout\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(16) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(15)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(15),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(16),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~46_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~47_combout\);

-- Location: FF_X48_Y46_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~47_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(1));

-- Location: FF_X48_Y46_N27
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~26\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(2),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\);

-- Location: LCCOMB_X48_Y46_N26
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~48\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~48_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~26_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a2\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~48_combout\);

-- Location: LCCOMB_X45_Y46_N12
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[18]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\);

-- Location: FF_X45_Y46_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[18]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(18));

-- Location: LCCOMB_X45_Y46_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[17]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \dbg_port_inst|hex_reader_inst|value\(2),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\);

-- Location: FF_X45_Y46_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[17]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(17));

-- Location: LCCOMB_X48_Y46_N12
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~49\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~49_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(18) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(17)))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~48_combout\)))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(18) & (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(17)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~48_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(18),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(17),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~49_combout\);

-- Location: FF_X48_Y46_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~49_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(2));

-- Location: LCCOMB_X46_Y46_N26
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[19]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(3),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\);

-- Location: FF_X46_Y46_N27
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[19]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(19));

-- Location: LCCOMB_X45_Y46_N22
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[20]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\);

-- Location: FF_X45_Y46_N23
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[20]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(20));

-- Location: FF_X48_Y46_N21
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~27\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(3),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\);

-- Location: LCCOMB_X48_Y46_N20
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~50\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~50_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~27_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a3\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~50_combout\);

-- Location: LCCOMB_X48_Y46_N22
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~51\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~51_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(20) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(19))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~50_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(20) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(19)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111010100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(19),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(20),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~50_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~51_combout\);

-- Location: FF_X48_Y46_N23
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~51_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(3));

-- Location: LCCOMB_X46_Y46_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[22]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\);

-- Location: FF_X46_Y46_N7
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[22]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(22));

-- Location: LCCOMB_X46_Y46_N20
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[21]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(4),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\);

-- Location: FF_X46_Y46_N21
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[21]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(21));

-- Location: FF_X48_Y46_N7
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~28\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(4),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\);

-- Location: LCCOMB_X48_Y46_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~52\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~52_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~28_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a4\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~52_combout\);

-- Location: LCCOMB_X48_Y46_N8
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~53\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~53_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(22) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(21))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~52_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(22) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(21)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(22),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(21),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~52_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~53_combout\);

-- Location: FF_X48_Y46_N9
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~53_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(4));

-- Location: LCCOMB_X46_Y46_N2
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[24]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\);

-- Location: FF_X46_Y46_N3
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[24]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[24]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(24));

-- Location: LCCOMB_X46_Y46_N0
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[23]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[23]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(5),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[23]~feeder_combout\);

-- Location: FF_X46_Y46_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[23]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[23]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(23));

-- Location: FF_X48_Y46_N25
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~29\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(5),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\);

-- Location: LCCOMB_X48_Y46_N24
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~54\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~54_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\)) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a5\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~29_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~54_combout\);

-- Location: LCCOMB_X47_Y46_N16
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~55\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~55_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(24) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(23))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~54_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(24) & (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(23)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(24),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(23),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~54_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~55_combout\);

-- Location: FF_X47_Y46_N17
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~55_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(5));

-- Location: LCCOMB_X46_Y46_N14
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[26]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[26]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[26]~feeder_combout\);

-- Location: FF_X46_Y46_N15
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[26]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[26]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(26));

-- Location: FF_X46_Y46_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[25]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(25));

-- Location: FF_X48_Y46_N19
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~30\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(6),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\);

-- Location: LCCOMB_X48_Y46_N18
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~56\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~56_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~30_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a6\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~56_combout\);

-- Location: LCCOMB_X47_Y46_N18
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~57\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~57_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(26) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(25))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~56_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(26) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(25)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(26),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(25),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~56_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~57_combout\);

-- Location: FF_X47_Y46_N19
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~57_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(6));

-- Location: LCCOMB_X47_Y46_N2
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[28]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[28]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[28]~feeder_combout\);

-- Location: FF_X47_Y46_N3
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[28]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[28]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(28));

-- Location: FF_X48_Y46_N29
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~31\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(7),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\);

-- Location: LCCOMB_X48_Y46_N28
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~58\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~58_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~31_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a7\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~58_combout\);

-- Location: LCCOMB_X47_Y46_N8
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[27]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[27]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(7),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[27]~feeder_combout\);

-- Location: FF_X47_Y46_N9
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[27]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[27]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(27));

-- Location: LCCOMB_X48_Y46_N2
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~59\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~59_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(28) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(27)))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~58_combout\)))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(28) & (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(27)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(28),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~58_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(27),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~59_combout\);

-- Location: FF_X48_Y46_N3
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~59_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(7));

-- Location: LCCOMB_X48_Y42_N2
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[30]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[30]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[30]~feeder_combout\);

-- Location: FF_X48_Y42_N3
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[30]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[30]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(30));

-- Location: FF_X49_Y42_N25
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~32\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(8),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\);

-- Location: LCCOMB_X49_Y42_N24
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~60\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~60_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a8\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~32_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a8\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~60_combout\);

-- Location: LCCOMB_X48_Y42_N8
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[29]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[29]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(8)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(8),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[29]~feeder_combout\);

-- Location: FF_X48_Y42_N9
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[29]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[29]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(29));

-- Location: LCCOMB_X49_Y42_N0
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~61\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~61_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(30) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(29)))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~60_combout\)))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(30) & (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(29)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(30),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~60_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(29),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~61_combout\);

-- Location: FF_X49_Y42_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~61_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(8));

-- Location: LCCOMB_X48_Y42_N14
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[32]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[32]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[32]~feeder_combout\);

-- Location: FF_X48_Y42_N15
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[32]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[32]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(32));

-- Location: FF_X49_Y42_N3
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~33\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(9),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\);

-- Location: LCCOMB_X49_Y42_N2
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~62\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~62_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a9\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~33_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a9\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~62_combout\);

-- Location: LCCOMB_X48_Y42_N12
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[31]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[31]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(9)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(9),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[31]~feeder_combout\);

-- Location: FF_X48_Y42_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[31]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[31]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(31));

-- Location: LCCOMB_X49_Y42_N26
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~63\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~63_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(32) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(31)))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~62_combout\)))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(32) & (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(31)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(32),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~62_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(31),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~63_combout\);

-- Location: FF_X49_Y42_N27
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~63_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(9));

-- Location: LCCOMB_X48_Y42_N26
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[34]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[34]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[34]~feeder_combout\);

-- Location: FF_X48_Y42_N27
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[34]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[34]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(34));

-- Location: LCCOMB_X48_Y42_N0
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[33]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[33]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(10)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(10),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[33]~feeder_combout\);

-- Location: FF_X48_Y42_N1
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[33]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[33]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(33));

-- Location: FF_X49_Y42_N13
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~34\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(10),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\);

-- Location: LCCOMB_X49_Y42_N12
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~64\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~64_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a10\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~34_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a10\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~64_combout\);

-- Location: LCCOMB_X49_Y42_N4
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~65\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~65_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(34) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(33))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~64_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(34) & (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(33)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(34),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(33),
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~64_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~65_combout\);

-- Location: FF_X49_Y42_N5
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~65_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(10));

-- Location: LCCOMB_X48_Y42_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[36]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[36]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[36]~feeder_combout\);

-- Location: FF_X48_Y42_N7
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[36]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[36]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(36));

-- Location: LCCOMB_X48_Y42_N4
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[35]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[35]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(11)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(11),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[35]~feeder_combout\);

-- Location: FF_X48_Y42_N5
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[35]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[35]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(35));

-- Location: FF_X49_Y42_N7
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~35\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(11),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\);

-- Location: LCCOMB_X49_Y42_N6
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~66\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~66_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a11\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~35_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a11\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~66_combout\);

-- Location: LCCOMB_X49_Y42_N22
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~67\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~67_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(36) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(35))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~66_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(36) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(35)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(36),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(35),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~66_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~67_combout\);

-- Location: FF_X49_Y42_N23
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~67_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(11));

-- Location: LCCOMB_X48_Y42_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[38]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[38]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[38]~feeder_combout\);

-- Location: FF_X48_Y42_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[38]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[38]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(38));

-- Location: FF_X48_Y42_N25
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[37]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(12),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(37));

-- Location: FF_X49_Y42_N17
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~36\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(12),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\);

-- Location: LCCOMB_X49_Y42_N16
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~68\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~68_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a12\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~36_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a12\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~68_combout\);

-- Location: LCCOMB_X49_Y42_N8
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~69\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~69_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(38) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(37))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~68_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(38) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(37)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111011000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(38),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(37),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~68_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~69_combout\);

-- Location: FF_X49_Y42_N9
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~69_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(12));

-- Location: LCCOMB_X48_Y42_N20
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[39]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[39]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(13)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(13),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[39]~feeder_combout\);

-- Location: FF_X48_Y42_N21
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[39]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[39]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(39));

-- Location: LCCOMB_X48_Y42_N22
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[40]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[40]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[40]~feeder_combout\);

-- Location: FF_X48_Y42_N23
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[40]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[40]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(40));

-- Location: FF_X49_Y42_N19
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~37\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(13),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\);

-- Location: LCCOMB_X49_Y42_N18
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~70\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~70_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a13\)) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a13\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~37_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~70_combout\);

-- Location: LCCOMB_X49_Y42_N10
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~71\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~71_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(40) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(39))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~70_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(40) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(39)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111010100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(39),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(40),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~70_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~71_combout\);

-- Location: FF_X49_Y42_N11
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~71_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(13));

-- Location: FF_X48_Y42_N17
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[41]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(14),
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(41));

-- Location: LCCOMB_X48_Y42_N18
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[42]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[42]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[42]~feeder_combout\);

-- Location: FF_X48_Y42_N19
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[42]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[42]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(42));

-- Location: FF_X49_Y42_N21
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~38\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(14),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\);

-- Location: LCCOMB_X49_Y42_N20
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~72\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~72_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a14\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~38_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a14\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~72_combout\);

-- Location: LCCOMB_X49_Y42_N28
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~73\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~73_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(42) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(41))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~72_combout\))))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(42) & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(41)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111010100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(41),
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(42),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~72_combout\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~73_combout\);

-- Location: FF_X49_Y42_N29
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~73_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(14));

-- Location: FF_X49_Y42_N31
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~39\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|hex_reader_inst|value\(15),
	sload => VCC,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~77_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\);

-- Location: LCCOMB_X49_Y42_N30
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~74\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~74_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a15\))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~23_q\,
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~39_q\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0|auto_generated|ram_block1a15\,
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~74_combout\);

-- Location: LCCOMB_X48_Y42_N30
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[44]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[44]~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[44]~feeder_combout\);

-- Location: FF_X48_Y42_N31
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[44]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[44]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(44));

-- Location: LCCOMB_X48_Y42_N28
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[43]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[43]~feeder_combout\ = \dbg_port_inst|hex_reader_inst|value\(15)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|hex_reader_inst|value\(15),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[43]~feeder_combout\);

-- Location: FF_X48_Y42_N29
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[43]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass[43]~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(43));

-- Location: LCCOMB_X49_Y42_N14
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~75\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~75_combout\ = (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(44) & ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & 
-- ((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(43)))) # (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\ & (\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~74_combout\)))) # 
-- (!\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(44) & (((\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(43)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~74_combout\,
	datab => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(44),
	datac => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~44_combout\,
	datad => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram_rtl_0_bypass\(43),
	combout => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~75_combout\);

-- Location: FF_X49_Y42_N15
\dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|ram~75_combout\,
	ena => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|ALT_INV_rd_int~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|gfx_data_fifo_inst|ci_fifo_inst|memory_inst|rd1_data\(15));

-- Location: LCCOMB_X49_Y46_N18
\dbg_port_inst|gfx_data_rd_ack\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|gfx_data_rd_ack~combout\ = (\dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\ & !\gfx_data_full~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|gfx_data_fifo_inst|rd_valid~q\,
	datad => \gfx_data_full~input_o\,
	combout => \dbg_port_inst|gfx_data_rd_ack~combout\);

-- Location: IOIBUF_X0_Y35_N8
\nes_latch~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_nes_latch,
	o => \nes_latch~input_o\);

-- Location: LCCOMB_X16_Y40_N16
\dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~0_combout\ = !\nes_latch~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \nes_latch~input_o\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~0_combout\);

-- Location: FF_X16_Y40_N17
\dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~q\);

-- Location: LCCOMB_X16_Y40_N10
\dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\ = (\nes_latch~input_o\ & \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_latch_old~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\);

-- Location: IOIBUF_X0_Y35_N15
\nes_clk~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_nes_clk,
	o => \nes_clk~input_o\);

-- Location: LCCOMB_X16_Y40_N26
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4_combout\ = (\nes_latch~input_o\ & \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4_combout\);

-- Location: LCCOMB_X16_Y40_N4
\dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~0_combout\ = !\nes_clk~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \nes_clk~input_o\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~0_combout\);

-- Location: FF_X16_Y40_N5
\dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~q\);

-- Location: LCCOMB_X16_Y40_N8
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\ = (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~q\ & \nes_clk~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010101000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|nes_clk_old~q\,
	datac => \nes_clk~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\);

-- Location: LCCOMB_X16_Y40_N6
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4_combout\) # ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111011101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~2_combout\);

-- Location: FF_X16_Y40_N7
\dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\);

-- Location: LCCOMB_X16_Y40_N20
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4_combout\) # ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~4_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~0_combout\);

-- Location: LCCOMB_X16_Y40_N2
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~1_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~0_combout\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3_combout\) # 
-- ((!\dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\ & \dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100010011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|state.INIT~q\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~1_combout\);

-- Location: FF_X16_Y40_N3
\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector1~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\);

-- Location: LCCOMB_X16_Y40_N22
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\nes_clk~input_o\) # ((!\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & 
-- \nes_latch~input_o\)))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (((\nes_latch~input_o\) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101011110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_clk~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\);

-- Location: LCCOMB_X16_Y40_N18
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\ & (((\nes_latch~input_o\ & \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\)) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\ & (((\nes_latch~input_o\ & \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001000100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\,
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3_combout\);

-- Location: LCCOMB_X16_Y40_N24
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~6_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\ & (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\ & (!\nes_latch~input_o\ & 
-- \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~2_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\,
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~6_combout\);

-- Location: LCCOMB_X16_Y40_N0
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~5_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~6_combout\) # ((!\dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\ & 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|nxt_state~0_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector0~3_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~3_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~6_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~5_combout\);

-- Location: FF_X16_Y40_N1
\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector2~5_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\);

-- Location: LCCOMB_X14_Y40_N16
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & ((\nes_latch~input_o\) # (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000011100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_latch~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~0_combout\);

-- Location: LCCOMB_X14_Y40_N18
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\ = (!\nes_latch~input_o\ & \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\);

-- Location: LCCOMB_X14_Y40_N10
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~1_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~0_combout\) # ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\ & ((\nes_clk~input_o\) # 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111011101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~0_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\,
	datac => \nes_clk~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~1_combout\);

-- Location: LCCOMB_X13_Y40_N18
\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~0_combout\ = \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0) $ (VCC)
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~1\ = CARRY(\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0),
	datad => VCC,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~0_combout\,
	cout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~1\);

-- Location: LCCOMB_X16_Y40_N30
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~4_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~0_combout\ $ 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~4_combout\);

-- Location: LCCOMB_X16_Y40_N14
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~7_combout\ = (\nes_latch~input_o\ & (((\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\)))) # (!\nes_latch~input_o\ & (\nes_clk~input_o\ & 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_clk~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~7_combout\);

-- Location: LCCOMB_X16_Y40_N28
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~6_combout\ = (!\nes_latch~input_o\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\) # ((!\nes_clk~input_o\ & 
-- \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110100001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_clk~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datac => \nes_latch~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~6_combout\);

-- Location: LCCOMB_X16_Y40_N12
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~5_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0) & (((!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~7_combout\)) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~4_combout\))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~6_combout\ & 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~4_combout\) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~7_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000001111011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~4_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~7_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~6_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~5_combout\);

-- Location: FF_X16_Y40_N13
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector9~5_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0));

-- Location: LCCOMB_X13_Y40_N20
\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~1\)) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1) & 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~1\) # (GND)))
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~3\ = CARRY((!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~1\) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1),
	datad => VCC,
	cin => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~1\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2_combout\,
	cout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~3\);

-- Location: LCCOMB_X13_Y40_N0
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~1_combout\ = (\nes_latch~input_o\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2_combout\)) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1)))))) # (!\nes_latch~input_o\ & (((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101111110000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_latch~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~1_combout\);

-- Location: LCCOMB_X13_Y40_N14
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & ((\nes_clk~input_o\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2_combout\))) # (!\nes_clk~input_o\ 
-- & (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1))))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~2_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datad => \nes_clk~input_o\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~0_combout\);

-- Location: LCCOMB_X13_Y40_N12
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~1_combout\) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~0_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\)))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & 
-- (((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~0_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~1_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~2_combout\);

-- Location: FF_X13_Y40_N13
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector8~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1));

-- Location: LCCOMB_X14_Y40_N22
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~3_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\ & ((\nes_clk~input_o\) # ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6))))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\ & (((\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_clk~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~3_combout\);

-- Location: LCCOMB_X14_Y40_N0
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & \nes_latch~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datac => \nes_latch~input_o\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0_combout\);

-- Location: LCCOMB_X14_Y40_N4
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & ((\nes_latch~input_o\) # (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000011100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_latch~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~0_combout\);

-- Location: LCCOMB_X14_Y40_N6
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~1_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~0_combout\) # ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\ & ((\nes_clk~input_o\) # 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111011101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~0_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\,
	datac => \nes_clk~input_o\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~1_combout\);

-- Location: LCCOMB_X13_Y40_N26
\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~8_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4) & (\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~7\ $ (GND))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4) & 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~7\ & VCC))
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~9\ = CARRY((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4) & !\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4),
	datad => VCC,
	cin => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~7\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~8_combout\,
	cout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~9\);

-- Location: LCCOMB_X13_Y40_N28
\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~10_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~9\)) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5) & 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~9\) # (GND)))
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~11\ = CARRY((!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~9\) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5),
	datad => VCC,
	cin => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~9\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~10_combout\,
	cout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~11\);

-- Location: LCCOMB_X14_Y40_N2
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~1_combout\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5)) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~10_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010100010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~1_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~10_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~2_combout\);

-- Location: FF_X14_Y40_N3
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector4~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5));

-- Location: LCCOMB_X13_Y40_N30
\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~12_combout\ = \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~11\ $ (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6),
	cin => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~11\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~12_combout\);

-- Location: LCCOMB_X14_Y40_N28
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~12_combout\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\ & 
-- ((!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0)) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~12_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~2_combout\);

-- Location: LCCOMB_X14_Y40_N24
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~4_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~3_combout\ & (((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6)) # 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~2_combout\)))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~3_combout\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0_combout\ & 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~2_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~3_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~2_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~4_combout\);

-- Location: FF_X14_Y40_N25
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~4_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6));

-- Location: LCCOMB_X14_Y40_N8
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ = (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6) & (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\ & 
-- ((!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0)) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\);

-- Location: LCCOMB_X13_Y40_N22
\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2) & (\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~3\ $ (GND))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2) & 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~3\ & VCC))
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~5\ = CARRY((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2) & !\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2),
	datad => VCC,
	cin => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~3\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4_combout\,
	cout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~5\);

-- Location: LCCOMB_X13_Y40_N2
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2)) # ((\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4_combout\ & (\nes_clk~input_o\ & 
-- \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111110000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4_combout\,
	datab => \nes_clk~input_o\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~0_combout\);

-- Location: LCCOMB_X13_Y40_N4
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~1_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2)) # ((\nes_latch~input_o\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & 
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111110000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_latch~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~4_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~1_combout\);

-- Location: LCCOMB_X13_Y40_N10
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~1_combout\) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~0_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\)))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~0_combout\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110110010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~1_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~2_combout\);

-- Location: FF_X13_Y40_N11
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector7~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2));

-- Location: LCCOMB_X13_Y40_N24
\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~6_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~5\)) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3) & 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~5\) # (GND)))
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~7\ = CARRY((!\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~5\) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3),
	datad => VCC,
	cin => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~5\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~6_combout\,
	cout => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~7\);

-- Location: LCCOMB_X14_Y40_N20
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~1_combout\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3)) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~6_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010100010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~1_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~6_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~2_combout\);

-- Location: FF_X14_Y40_N21
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector6~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3));

-- Location: LCCOMB_X13_Y40_N6
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4)) # (\nes_latch~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010100010101000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|state.PARALLEL_LOAD~q\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4),
	datac => \nes_latch~input_o\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~0_combout\);

-- Location: LCCOMB_X13_Y40_N16
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~1_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~0_combout\) # ((\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\ & ((\nes_clk~input_o\) # 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~0_combout\,
	datab => \nes_clk~input_o\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~1_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~1_combout\);

-- Location: LCCOMB_X13_Y40_N8
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~1_combout\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4)) # 
-- ((\dbg_port_inst|nes:nes_controller_emulator_inst|Add1~8_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Add1~8_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_next~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~1_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~2_combout\);

-- Location: FF_X13_Y40_N9
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector5~2_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4));

-- Location: LCCOMB_X14_Y40_N30
\dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\ = (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2) & 
-- !\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(4),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(3),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(2),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(5),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\);

-- Location: LCCOMB_X14_Y40_N26
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~0_combout\ = ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6)) # (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111011101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~0_combout\);

-- Location: LCCOMB_X18_Y45_N12
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~feeder_combout\ = \dbg_port_inst|nes_buttons_intern\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes_buttons_intern\(6),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~feeder_combout\);

-- Location: FF_X18_Y45_N13
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~q\);

-- Location: FF_X18_Y45_N3
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_right\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|nes_buttons_intern\(7),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_right~q\);

-- Location: LCCOMB_X18_Y45_N2
\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~2_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~q\ & (\dbg_port_inst|nes_buttons_intern\(6) & (\dbg_port_inst|nes_buttons_intern\(7) $ 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_right~q\)))) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~q\ & (!\dbg_port_inst|nes_buttons_intern\(6) & (\dbg_port_inst|nes_buttons_intern\(7) $ 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_right~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000001001000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_left~q\,
	datab => \dbg_port_inst|nes_buttons_intern\(7),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_right~q\,
	datad => \dbg_port_inst|nes_buttons_intern\(6),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~2_combout\);

-- Location: FF_X14_Y45_N5
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_b\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|nes_buttons_intern\(1),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_b~q\);

-- Location: LCCOMB_X18_Y45_N24
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~feeder_combout\ = \dbg_port_inst|nes_buttons_intern\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes_buttons_intern\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~feeder_combout\);

-- Location: FF_X18_Y45_N25
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~q\);

-- Location: LCCOMB_X14_Y45_N4
\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~1_combout\ = (\dbg_port_inst|nes_buttons_intern\(1) & (\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_b~q\ & (\dbg_port_inst|nes_buttons_intern\(0) $ 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~q\)))) # (!\dbg_port_inst|nes_buttons_intern\(1) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_b~q\ & (\dbg_port_inst|nes_buttons_intern\(0) $ 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(1),
	datab => \dbg_port_inst|nes_buttons_intern\(0),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_b~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_a~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~1_combout\);

-- Location: FF_X14_Y45_N9
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_up\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|nes_buttons_intern\(4),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_up~q\);

-- Location: LCCOMB_X14_Y45_N30
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~feeder_combout\ = \dbg_port_inst|nes_buttons_intern\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes_buttons_intern\(5),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~feeder_combout\);

-- Location: FF_X14_Y45_N31
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~q\);

-- Location: LCCOMB_X14_Y45_N8
\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~3_combout\ = (\dbg_port_inst|nes_buttons_intern\(4) & (\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_up~q\ & (\dbg_port_inst|nes_buttons_intern\(5) $ 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~q\)))) # (!\dbg_port_inst|nes_buttons_intern\(4) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_up~q\ & (\dbg_port_inst|nes_buttons_intern\(5) $ 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(4),
	datab => \dbg_port_inst|nes_buttons_intern\(5),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_up~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_down~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~3_combout\);

-- Location: LCCOMB_X14_Y45_N18
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~feeder_combout\ = \dbg_port_inst|nes_buttons_intern\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes_buttons_intern\(3),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~feeder_combout\);

-- Location: FF_X14_Y45_N19
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~q\);

-- Location: FF_X14_Y45_N17
\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_select\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \dbg_port_inst|nes_buttons_intern\(2),
	clrn => \res_n~inputclkctrl_outclk\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_select~q\);

-- Location: LCCOMB_X14_Y45_N16
\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~0_combout\ = (\dbg_port_inst|nes_buttons_intern\(2) & (\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_select~q\ & 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~q\ $ (!\dbg_port_inst|nes_buttons_intern\(3))))) # (!\dbg_port_inst|nes_buttons_intern\(2) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_select~q\ & 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~q\ $ (!\dbg_port_inst|nes_buttons_intern\(3)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000010000100001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(2),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_start~q\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|button_state_old.btn_select~q\,
	datad => \dbg_port_inst|nes_buttons_intern\(3),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~0_combout\);

-- Location: LCCOMB_X14_Y45_N2
\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~2_combout\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~1_combout\ & 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~3_combout\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~2_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~1_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~3_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~0_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4_combout\);

-- Location: LCCOMB_X14_Y44_N10
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[0]~1_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4_combout\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(1) $ 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(1),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(0),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[0]~1_combout\);

-- Location: FF_X14_Y44_N11
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[0]~1_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(0));

-- Location: LCCOMB_X14_Y44_N16
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[1]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[1]~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4_combout\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(0)) # 
-- (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(0),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(1),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal0~4_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[1]~0_combout\);

-- Location: FF_X14_Y44_N17
\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state[1]~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(1));

-- Location: LCCOMB_X14_Y40_N12
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1_combout\ = (((\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~0_combout\) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(1))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0_combout\)) # (!\dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111011111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector3~0_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt_button_state\(1),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1_combout\);

-- Location: LCCOMB_X14_Y40_N14
\dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1) & (!\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6) & (\dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\ & 
-- !\dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(1),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(6),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~0_combout\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|cnt\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1_combout\);

-- Location: LCCOMB_X14_Y45_N22
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector10~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector10~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\nes_clk~input_o\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1_combout\)))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (((!\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010001100000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_clk~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector10~0_combout\);

-- Location: LCCOMB_X14_Y45_N12
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[7]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[7]~3_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|Selector10~0_combout\ & (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes_buttons_intern\(7)))) 
-- # (!\dbg_port_inst|nes:nes_controller_emulator_inst|Selector10~0_combout\ & (((\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(7)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100010011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	datab => \dbg_port_inst|nes_buttons_intern\(7),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(7),
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector10~0_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[7]~3_combout\);

-- Location: FF_X14_Y45_N13
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[7]~3_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(7));

-- Location: LCCOMB_X14_Y45_N10
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector11~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(7))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\dbg_port_inst|nes_buttons_intern\(6))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(7),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|nes_buttons_intern\(6),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector11~0_combout\);

-- Location: LCCOMB_X14_Y45_N20
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\ = ((\nes_clk~input_o\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1_combout\))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011001100110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \nes_clk~input_o\,
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~1_combout\,
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|Equal1~1_combout\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\);

-- Location: FF_X14_Y45_N11
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector11~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(6));

-- Location: LCCOMB_X14_Y45_N24
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector12~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector12~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(6)))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes_buttons_intern\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \dbg_port_inst|nes_buttons_intern\(5),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(6),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector12~0_combout\);

-- Location: FF_X14_Y45_N25
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector12~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(5));

-- Location: LCCOMB_X14_Y45_N14
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector13~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector13~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(5)))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes_buttons_intern\(4)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(4),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(5),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector13~0_combout\);

-- Location: FF_X14_Y45_N15
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector13~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(4));

-- Location: LCCOMB_X14_Y45_N28
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector14~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector14~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(4)))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes_buttons_intern\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101011001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(3),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(4),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector14~0_combout\);

-- Location: FF_X14_Y45_N29
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector14~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(3));

-- Location: LCCOMB_X14_Y45_N6
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector15~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector15~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(3)))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes_buttons_intern\(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101011001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(2),
	datab => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(3),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector15~0_combout\);

-- Location: FF_X14_Y45_N7
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector15~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(2));

-- Location: LCCOMB_X14_Y45_N26
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector16~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector16~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(2)))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes_buttons_intern\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes_buttons_intern\(1),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(2),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector16~0_combout\);

-- Location: FF_X14_Y45_N27
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector16~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(1));

-- Location: LCCOMB_X14_Y45_N0
\dbg_port_inst|nes:nes_controller_emulator_inst|Selector17~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|Selector17~0_combout\ = (\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & (\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(1))) # 
-- (!\dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\ & ((\dbg_port_inst|nes_buttons_intern\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010110010101100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(1),
	datab => \dbg_port_inst|nes_buttons_intern\(0),
	datac => \dbg_port_inst|nes:nes_controller_emulator_inst|state.SHIFT~q\,
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector17~0_combout\);

-- Location: FF_X14_Y45_N1
\dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|Selector17~0_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	ena => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg[6]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(0));

-- Location: LCCOMB_X5_Y45_N6
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[0]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[0]~feeder_combout\ = \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|shift_reg\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[0]~feeder_combout\);

-- Location: FF_X5_Y45_N7
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[0]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(0));

-- Location: LCCOMB_X5_Y45_N12
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[1]~feeder_combout\ = \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(0),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[1]~feeder_combout\);

-- Location: FF_X5_Y45_N13
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[1]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(1));

-- Location: LCCOMB_X5_Y45_N10
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[2]~feeder_combout\ = \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(1),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[2]~feeder_combout\);

-- Location: FF_X5_Y45_N11
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[2]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(2));

-- Location: LCCOMB_X5_Y45_N24
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[3]~feeder_combout\ = \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(2),
	combout => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[3]~feeder_combout\);

-- Location: FF_X5_Y45_N25
\dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay[3]~feeder_combout\,
	clrn => \res_n~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \dbg_port_inst|nes:nes_controller_emulator_inst|output_delay\(3));

ww_tx <= \tx~output_o\;

ww_switches(0) <= \switches[0]~output_o\;

ww_switches(1) <= \switches[1]~output_o\;

ww_switches(2) <= \switches[2]~output_o\;

ww_switches(3) <= \switches[3]~output_o\;

ww_switches(4) <= \switches[4]~output_o\;

ww_switches(5) <= \switches[5]~output_o\;

ww_switches(6) <= \switches[6]~output_o\;

ww_switches(7) <= \switches[7]~output_o\;

ww_switches(8) <= \switches[8]~output_o\;

ww_switches(9) <= \switches[9]~output_o\;

ww_switches(10) <= \switches[10]~output_o\;

ww_switches(11) <= \switches[11]~output_o\;

ww_switches(12) <= \switches[12]~output_o\;

ww_switches(13) <= \switches[13]~output_o\;

ww_switches(14) <= \switches[14]~output_o\;

ww_switches(15) <= \switches[15]~output_o\;

ww_switches(16) <= \switches[16]~output_o\;

ww_switches(17) <= \switches[17]~output_o\;

ww_keys(0) <= \keys[0]~output_o\;

ww_keys(1) <= \keys[1]~output_o\;

ww_keys(2) <= \keys[2]~output_o\;

ww_keys(3) <= \keys[3]~output_o\;

ww_dsc <= \dsc~output_o\;

ww_gfx_instr(0) <= \gfx_instr[0]~output_o\;

ww_gfx_instr(1) <= \gfx_instr[1]~output_o\;

ww_gfx_instr(2) <= \gfx_instr[2]~output_o\;

ww_gfx_instr(3) <= \gfx_instr[3]~output_o\;

ww_gfx_instr(4) <= \gfx_instr[4]~output_o\;

ww_gfx_instr(5) <= \gfx_instr[5]~output_o\;

ww_gfx_instr(6) <= \gfx_instr[6]~output_o\;

ww_gfx_instr(7) <= \gfx_instr[7]~output_o\;

ww_gfx_instr_wr <= \gfx_instr_wr~output_o\;

ww_gfx_data(0) <= \gfx_data[0]~output_o\;

ww_gfx_data(1) <= \gfx_data[1]~output_o\;

ww_gfx_data(2) <= \gfx_data[2]~output_o\;

ww_gfx_data(3) <= \gfx_data[3]~output_o\;

ww_gfx_data(4) <= \gfx_data[4]~output_o\;

ww_gfx_data(5) <= \gfx_data[5]~output_o\;

ww_gfx_data(6) <= \gfx_data[6]~output_o\;

ww_gfx_data(7) <= \gfx_data[7]~output_o\;

ww_gfx_data(8) <= \gfx_data[8]~output_o\;

ww_gfx_data(9) <= \gfx_data[9]~output_o\;

ww_gfx_data(10) <= \gfx_data[10]~output_o\;

ww_gfx_data(11) <= \gfx_data[11]~output_o\;

ww_gfx_data(12) <= \gfx_data[12]~output_o\;

ww_gfx_data(13) <= \gfx_data[13]~output_o\;

ww_gfx_data(14) <= \gfx_data[14]~output_o\;

ww_gfx_data(15) <= \gfx_data[15]~output_o\;

ww_gfx_data_wr <= \gfx_data_wr~output_o\;

ww_nes_buttons_btn_up <= \nes_buttons_btn_up~output_o\;

ww_nes_buttons_btn_down <= \nes_buttons_btn_down~output_o\;

ww_nes_buttons_btn_left <= \nes_buttons_btn_left~output_o\;

ww_nes_buttons_btn_right <= \nes_buttons_btn_right~output_o\;

ww_nes_buttons_btn_start <= \nes_buttons_btn_start~output_o\;

ww_nes_buttons_btn_select <= \nes_buttons_btn_select~output_o\;

ww_nes_buttons_btn_a <= \nes_buttons_btn_a~output_o\;

ww_nes_buttons_btn_b <= \nes_buttons_btn_b~output_o\;

ww_nes_data <= \nes_data~output_o\;
END structure;


